公开(公告)号：US20200244908A1

公开(公告)日：2020-07-30

申请号：US16737527

申请日：2020-01-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Osamu MATSUMOTO ,  Masanori OTSUKA ,  Fukashi MORISHITA

IPC: H04N5/378 ,  H03M1/56 ,  H03K5/24 ,  H03M1/34 ,  H04N5/351

Abstract: A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.

公开(公告)号：US20180007301A1

公开(公告)日：2018-01-04

申请号：US15704997

申请日：2017-09-14

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro UEDA ,  Fukashi MORISHITA

IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/347

CPC classification number: H04N5/378 ,  H04N5/347 ,  H04N5/37457

Abstract: A semiconductor device includes a pixel array including a plurality of pixels arranged in a matrix, each pixel including a first switch and a second switch, a scanning circuit, in a first mode, enabling a first signal to be output from the pixel by setting the first and second switches to “off” in a period before a first timing, enabling a second signal to be output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and enabling a third signal to be output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing, and a first AD (Analog/Digital) converter, in a second mode, capable of performing AD conversion by comparing the difference between the second signal and the first signal with a reference signal.

公开(公告)号：US20230412947A1

公开(公告)日：2023-12-21

申请号：US18319152

申请日：2023-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi IIZUKA ,  Fukashi MORISHITA

IPC: H04N25/772

CPC classification number: H04N25/772

Abstract: A solid-state image sensor includes a buffer circuit, and an AD conversion circuit. The buffer circuit is connected to a first pixel and a second pixel of a plurality of pixels. The AD conversion circuit converts a voltage signal from the buffer circuit into a digital signal. The buffer circuit includes a voltage holding circuit connected to the first pixel, a voltage holding circuit connected to the second pixel, and a switch circuit. The switch circuit selectively switches the voltage holding circuit which outputs a voltage signal to the AD conversion circuit between the voltage holding circuits. The buffer circuit carries out an operation of holding a voltage signal of the first pixel in the voltage holding circuit and an operation of holding a voltage signal of the second pixel in the voltage holding circuit in parallel with each other.

公开(公告)号：US20220408046A1

公开(公告)日：2022-12-22

申请号：US17841183

申请日：2022-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Norihito KATOU ,  Fukashi MORISHITA

IPC: H04N5/378 ,  H04N5/3745

Abstract: A technique capable of improving linearity at a low illuminance is provided. A solid-state sensing image device includes: a pixel array including a plurality pixels arranged in a matrix form and a plurality of pixel signal lines connected to the plurality of pixels and receiving pixel signals supplied from the plurality pixels; a column-parallel A/D converting circuit connected to the plurality of pixel signal lines; and a reference-voltage generating circuit generating ramp-wave reference voltage that linearly changes in accordance with time passage. The column-parallel A/D converting circuit includes a first A/D converter, the first A/D converter includes: a first input terminal connected to the pixel signal line; a second input terminal receiving the reference voltage; and an offset generating circuit connected to the first input terminal and generating an offset voltage for the first input terminal.

公开(公告)号：US20170302875A1

公开(公告)日：2017-10-19

申请号：US15634377

申请日：2017-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunsuke OKURA ,  Fukashi MORISHITA

IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/378

CPC classification number: H04N5/37457 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/378

Abstract: The present invention makes it possible to read a pixel signal at high speed. A pixel array includes a plurality of pixels that store an electrical charge. The amount of stored electrical charge is based on the amount of received light. A first pixel current source and a second pixel current source are coupled in parallel between a ground voltage and a pixel output node on a pixel signal read line. A switch is disposed in a wiring path that couples the pixel output node, the second pixel current source, and the ground voltage.

公开(公告)号：US20150236712A1

公开(公告)日：2015-08-20

申请号：US14702492

申请日：2015-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunsuke OKURA ,  Fukashi MORISHITA

IPC: H03M1/46 ,  H04N5/378

CPC classification number: H03M1/468 ,  H03M1/38 ,  H03M1/46 ,  H03M1/804 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/378

Abstract: The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n−1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/D conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n−1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.

Abstract translation: 本发明提供一种小型便宜的固态成像装置。 包括在固态成像装置的连续比较型A / D转换器中的AD / A转换器包括多路复用器，其选择参考电压VR0至VR16中的任何一个，并且当执行粗略A / D转换时将其设置为模拟参考信号， 并且当执行精细的A / D转换时，其选择参考电压VR0至VR16的参考电压VR（n-1）至VR（n + 2），以及基于参考电压产生模拟参考信号的电容器阵列 当进行精细的A / D转换时，VR（n-1）至VR（n + 2）。 因此，可以在不使用冗余电容器的情况下降低参考电压的稳定误差。

公开(公告)号：US20230138391A1

公开(公告)日：2023-05-04

申请号：US17978266

申请日：2022-11-01

Applicant: Renesas Electronics Corporation

Inventor： Wataru SAITO ,  Fukashi MORISHITA

IPC: H03M1/10

Abstract: A semiconductor device includes a digital-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-analog converter to test the digital-analog converter. The test circuit includes: a charge information holding circuit that holds, as differential charge information, a difference value between a first charge according to a first current and a second charge according to a second current by at least one or more current cells among the plurality of current cells; a reference voltage generation circuit that generates a reference voltage to be comparative object; and a comparison circuit that compares a determination voltage according to the differential charge information and the reference voltage to output a comparison result.

公开(公告)号：US20230087101A1

公开(公告)日：2023-03-23

申请号：US17886033

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi IIZUKA ,  Fukashi MORISHITA

IPC: H03M1/36 ,  H03K23/54 ,  H03M1/08 ,  H03M1/50 ,  H03K23/44

Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

公开(公告)号：US20170118433A1

公开(公告)日：2017-04-27

申请号：US15398246

申请日：2017-01-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunsuke OKURA ,  Fukashi MORISHITA

IPC: H04N5/378 ,  H04N5/376 ,  H04N5/363

CPC classification number: H04N5/378 ,  H04N5/363 ,  H04N5/374 ,  H04N5/3765

Abstract: The present invention provides a technique for achieving higher picture quality of a captured image by reducing noise which occurs at the time of resetting in a solid-state image sensing device and the like. A pixel array in a solid-state image sensing device includes a plurality of pixels and includes an OB pixel region and an effective pixel region. The solid-state image sensing device has a signal processing unit outputting a pixel signal of each of the pixels in the effective pixel region on the basis of the signal level of a signal output from each of the pixels. The solid-state image sensing device obtains a signal without applying a reset signal to each of the pixels in the OB pixel region, obtains the difference between the signal and a signal of a pixel in the effective pixel region, and outputs an image signal.

公开(公告)号：US20140226049A1

公开(公告)日：2014-08-14

申请号：US14256680

申请日：2014-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto UTSUNOMIYA ,  Katsumi DOSAKA ,  Hiroshi KATO ,  Fukashi MORISHITA ,  Fumiyasu SASAKI

IPC: H04N5/369

CPC classification number: H04N5/37455 ,  H03M1/1205 ,  H03M1/144 ,  H03M1/403 ,  H03M1/66 ,  H03M2201/16 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。