公开(公告)号：US20230297528A1

公开(公告)日：2023-09-21

申请号：US18152582

申请日：2023-01-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Rajesh GHIMIRE

IPC: G06F13/28 ,  G06F13/16 ,  G06F7/544

CPC classification number: G06F13/28 ,  G06F13/1689 ,  G06F7/5443

Abstract: A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.

公开(公告)号：US20240104034A1

公开(公告)日：2024-03-28

申请号：US18348534

申请日：2023-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TERASHIMA ,  Atsushi NAKAMURA ,  Rajesh GHIMIRE

IPC: G06F13/28 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F13/28 ,  G06T1/20 ,  G06T1/60

Abstract: A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.