公开(公告)号：US20150325696A1

公开(公告)日：2015-11-12

申请号：US14804819

申请日：2015-07-21

Applicant: Renesas Electronics Corporation

Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

公开(公告)号：US20150270385A1

公开(公告)日：2015-09-24

申请号：US14642793

申请日：2015-03-10

Applicant: Renesas Electronics Corporation

Inventor： Saya SHIMOMURA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

Abstract: To enhance a semiconductor device. A semiconductor device has a plurality of p+-type semiconductor regions disposed between the mutually adjacent two gate trenches, in a cell region. The p+ type semiconductor regions are disposed spaced apart from each other, in plan view, in a p-type body layer in a portion positioned between the mutually adjacent two gate trenches. Any of a p-type impurity concentration in each of the p+ type semiconductor regions is higher than the p-type impurity concentration in the p-type body layer.

Abstract translation: 增强半导体器件。 半导体器件在单元区域中具有设置在相互相邻的两个栅极沟槽之间的多个p +型半导体区域。 p +型半导体区域在平面图中彼此间隔开设置在位于相互相邻的两个栅极沟槽之间的部分中的p型体层中。 p +型半导体区域中的每一个中的p型杂质浓度中的任何一个都高于p型体层中的p型杂质浓度。

公开(公告)号：US20140284709A1

公开(公告)日：2014-09-25

申请号：US14204145

申请日：2014-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。