公开(公告)号：US20240312969A1

公开(公告)日：2024-09-19

申请号：US18588091

申请日：2024-02-27

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Tatsuo KASAOKA ,  Yasutaka NAKASHIBA

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L24/48 ,  H01L2224/48195 ,  H01L2924/1206

Abstract: A semiconductor chip includes a semiconductor substrate and a multilayer wiring layer formed on the semiconductor substrate, and at least one layer of the multilayer wiring layer is formed with a conductive pattern. The conductive pattern is formed so as to continuously surround a lower inductor and an upper inductor in plan view.

公开(公告)号：US20240162144A1

公开(公告)日：2024-05-16

申请号：US18510633

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA ,  Tatsuo KASAOKA

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48464 ,  H01L2924/30101

Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer formed on the semiconductor substrate, a first wiring formed on the multilayer wiring layer and configured to be applied with a first potential, an upper inductor formed on the multilayer wiring layer and configured to be applied with a second potential different from the first potential, an inorganic insulating film formed on the multilayer wiring layer, the first wiring, and the upper inductor, and an organic insulating film formed on the inorganic insulating film and disposed so as to cover the inorganic insulating film located between the first wiring and the upper inductor in plan view. Here, between the first wiring and the upper inductor, an opening portion exposing a part of the upper surface of the inorganic insulating film is formed in the organic insulating film.

公开(公告)号：US20240096788A1

公开(公告)日：2024-03-21

申请号：US18344431

申请日：2023-06-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Tatsuo KASAOKA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5227 ,  H01L23/5283 ,  H01L23/53257

Abstract: A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

公开(公告)号：US20160013239A1

公开(公告)日：2016-01-14

申请号：US14747065

申请日：2015-06-23

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo KASAOKA

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14689

Abstract: Disclosed are a semiconductor device and a method for manufacturing the semiconductor device that is capable of adequately reducing the influence of inter-wiring capacitance even when a photoelectric conversion element is progressively miniaturized. A plurality of transfer transistors each include a photoelectric conversion element and a signal output section. A plurality of other transistors include at least one signal input/output section that is electrically coupled to the transfer transistors. An interlayer insulating film is formed so as to cover the transfer transistors and the other transistors. A total of at least three of at least one signal output section of the transfer transistors and at least one signal input/output section of the other transistors are coupled by a coupling layer that includes a conductor filled into a groove formed in the interlayer insulating film.

Abstract translation: 公开了即使当光电转换元件逐渐小型化时，也能够充分地减小布线间电容的影响的半导体器件和半导体器件的制造方法。 多个转移晶体管各自包括光电转换元件和信号输出部。 多个其它晶体管包括电耦合到传输晶体管的至少一个信号输入/输出部分。 形成层间绝缘膜以覆盖转移晶体管和其它晶体管。 转移晶体管的至少一个信号输出部分中的至少三个和其它晶体管的至少一个信号输入/输出部分中的至少三个通过耦合层耦合，所述耦合层包括填充到形成在层间绝缘膜中的沟槽中的导体 。

公开(公告)号：US20140252441A1

公开(公告)日：2014-09-11

申请号：US14287862

申请日：2014-05-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi HACHISUKA ,  Atsushi AMO ,  Tatsuo KASAOKA ,  Shunji KUBO

IPC: H01L27/108

CPC classification number: H01L27/10829 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract translation: 提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。 半导体器件包括半导体衬底和半导体衬底上的绝缘层，绝缘层中的多个接触插塞以及形成电容器，多个接触插塞，阻挡金属层和铜互连的绝缘层。 半导体衬底的上表面中的源/漏区电连接到铜互连。 在半导体衬底的上表面中的相邻源极/漏极区域中的一个电连接到铜互连，而另一个电连接到电容器。