公开(公告)号：US20140235020A1

公开(公告)日：2014-08-21

申请号：US14261497

申请日：2014-04-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke ARAI ,  Yoshito NAKAZAWA ,  Ikuo HARA ,  Tsuyoshi KACHI ,  Yoshinori HOSHINO ,  Tsuyoshi TABATA

IPC: H01L29/66

CPC classification number: H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract translation: 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。