公开(公告)号：US20130334542A1

公开(公告)日：2013-12-19

申请号：US13970586

申请日：2013-08-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Yasuaki KAGOTOSHI ,  Nobuo MACHIDA ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/36

CPC classification number: H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

公开(公告)号：US20170229557A1

公开(公告)日：2017-08-10

申请号：US15499578

申请日：2017-04-27

Applicant: Renesas Electronics Corporation

Inventor： Masaki HAMA ,  Yasuaki KAGOTOSHI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L21/04

CPC classification number: H01L29/66734 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor device includes carrying out a first heat treatment accompanied by nitration on a first insulating film and a silicon carbide substrate in a first gas atmosphere, after the carrying out of the first heat treatment and after a temperature of the silicon carbide substrate has become 700° C. or less, removing the silicon carbide substrate from a processing apparatus and exposing the silicon carbide substrate to air in an atmosphere outside of the processing apparatus, and after the exposing of the silicon carbide substrate to air in the atmosphere, carrying out a second heat treatment on the first insulating film and the silicon carbide substrate in a second gas atmosphere which is an inert gas.

公开(公告)号：US20160225892A1

公开(公告)日：2016-08-04

申请号：US15095469

申请日：2016-04-11

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Masaki HAMA ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

公开(公告)号：US20150236089A1

公开(公告)日：2015-08-20

申请号：US14706329

申请日：2015-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki KAGOTOSHI ,  Koichi ARAI ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。

公开(公告)号：US20150380541A1

公开(公告)日：2015-12-31

申请号：US14750196

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Masaki HAMA ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

Abstract translation: 本发明可以通过在湿蚀刻上在衬底上打开绝缘膜来指定在SiC衬底上形成的垂直型功率MOSFET的有源区，提高湿式蚀刻的精度​​和使半导体器件的小型化。 在外延层上依次形成膜厚小的氧化硅膜和膜厚度大于氧化硅膜的多晶硅膜，通过干式蚀刻方法打开多晶硅膜，依次将氧化硅膜为 通过湿蚀刻方法打开，从而暴露有源区中的外延层的上表面。

公开(公告)号：US20150035015A1

公开(公告)日：2015-02-05

申请号：US14325614

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi ARAI ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/66 ,  H01L29/808

CPC classification number: H01L29/8083 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.

Abstract translation: 提供具有非常优异的截止状态的垂直JFET的半导体器件，而不降低产量。 通过杂质离子注入在源极区的下方形成沿通道宽度方向的截面中四边形的栅极区域。 通过首先蚀刻，去除栅极区域的上表面上方的源极区域以在其间分离。 然后，栅极区域的上表面通过第二蚀刻进行处理，其蚀刻速率在侧表面比栅极区域的中心低。 所得到的栅极区域具有平行于基板表面的下表面和源区域和沟道形成区域之间的边界下方的上表面，并且在沿着沟道宽度方向的横截面中，从侧表面 到中心 结果，可以获得具有减小的变化的通道长度。

公开(公告)号：US20140284625A1

公开(公告)日：2014-09-25

申请号：US14220447

申请日：2014-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki KAGOTOSHI ,  Koichi ARAI ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/808 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。