公开(公告)号：US10134869B2

公开(公告)日：2018-11-20

申请号：US15368625

申请日：2016-12-04

Applicant: Renesas Electronics Corporation

Inventor： Yasufumi Morimoto ,  Kiyonobu Takahashi ,  Morihiko Kume

IPC: H01L29/66 ,  H01L21/822 ,  H01L49/02 ,  H01L21/02 ,  H01L21/285 ,  H01L21/265 ,  H01L21/311 ,  H01L21/324 ,  H01L27/06

Abstract: To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

公开(公告)号：US09117849B2

公开(公告)日：2015-08-25

申请号：US14325472

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

Abstract translation: 一种形成非易失性半导体器件的方法和装置，包括在第一半导体区域的主表面上形成第一栅极绝缘膜，在第一栅极绝缘膜上形成第一栅电极，形成第二栅极绝缘膜，形成第二栅极 电极，在第一栅电极的第一侧表面上，选择性地去除第二栅极绝缘膜，蚀刻保持在第二栅极电极和第一半导体区域的主表面之间的第二栅极绝缘膜，以形成蚀刻电荷存储层 为了形成第二半导体区域，以自对准的方式将第一半导体区域中的第一杂质引入第二栅电极，使半导体衬底退火，将第二半导体区域延伸到第二栅电极下方的区域。

公开(公告)号：US20140322874A1

公开(公告)日：2014-10-30

申请号：US14325472

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract translation: 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。