公开(公告)号：US20200020799A1

公开(公告)日：2020-01-16

申请号：US16446044

申请日：2019-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki UEDA ,  Satoru TOKUDA ,  Satoshi UCHIYA ,  Hiroyoshi KUDOU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device capable of reducing the influence of noise and easily securing a breakdown voltage between a source wiring and a drain wiring constituting a capacitance between a source and a drain even when shrinkage of a cell progresses, and a manufacturing method thereof are provided. The drain wiring is electrically connected to a substrate region, and the drain wiring is disposed in contact with an upper surface of an interlayer insulating layer. The source wiring is electrically connected to source regions and are disposed in contact with the upper surface of the interlayer insulating layer. A plurality of MOSFET cells are arranged side by side in a X-direction. The drain wiring and the source wiring extends in the X direction and are adjacent to each other in a Y direction crossing the X direction to form a capacitor.