公开(公告)号：US20240162221A1

公开(公告)日：2024-05-16

申请号：US18471662

申请日：2023-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyoshi KUDOU ,  Hideki NIWAYAMA

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L28/20 ,  H01L29/063 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved, and a decrease in yield is suppressed. A hard mask is formed on an upper surface of a semiconductor substrate. A trench is formed in the semiconductor substrate exposed out from the hard mask. A gate insulating film is formed in the trench. A conductive film is formed on the gate insulating film and the hard mask. The conductive film on the hard mask is removed, and a gate electrode is formed in the trench. A cap film is formed on an upper surface of the gate electrode. The hard mask is removed. A gate insulating film is formed on the upper surface of the semiconductor substrate. A conductive film is formed on the gate insulating film and the cap film. The conductive film on the cap film is removed, and a gate electrode is formed on the gate insulating film.

公开(公告)号：US20200020799A1

公开(公告)日：2020-01-16

申请号：US16446044

申请日：2019-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki UEDA ,  Satoru TOKUDA ,  Satoshi UCHIYA ,  Hiroyoshi KUDOU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device capable of reducing the influence of noise and easily securing a breakdown voltage between a source wiring and a drain wiring constituting a capacitance between a source and a drain even when shrinkage of a cell progresses, and a manufacturing method thereof are provided. The drain wiring is electrically connected to a substrate region, and the drain wiring is disposed in contact with an upper surface of an interlayer insulating layer. The source wiring is electrically connected to source regions and are disposed in contact with the upper surface of the interlayer insulating layer. A plurality of MOSFET cells are arranged side by side in a X-direction. The drain wiring and the source wiring extends in the X direction and are adjacent to each other in a Y direction crossing the X direction to form a capacitor.

公开(公告)号：US20170222039A1

公开(公告)日：2017-08-03

申请号：US15421920

申请日：2017-02-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Hiroyoshi KUDOU

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, and a gate electrode. The semiconductor substrate has a trench in the main surface. The gate electrode is formed in the trench. A distribution of an impurity concentration in the base region has a plurality of peak values along a direction of depth from the main surface toward the back surface, and the number of peak values is four or more.

公开(公告)号：US20160027916A1

公开(公告)日：2016-01-28

申请号：US14876765

申请日：2015-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki KATOU ,  Hiroyoshi KUDOU ,  Taro MORIYA ,  Satoshi UCHIYA

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0865 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

Abstract: Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Abstract translation: 沟槽形成在基层中并且彼此平行延伸。 在多个沟槽的每个的内壁上形成栅极绝缘膜。 栅电极GE被埋在每个沟槽中。 源层在基底层中形成到比基底层更深的深度。 源层设置在每个沟槽之间。 在平面图中，在源极层和沟槽之间形成第二导电型高浓度层。 沟槽，源极层和第二导电型高浓度以平面图重复排列。 沟槽的一个侧面面向源极层，沟槽的另一个侧面面向第二导电型高浓度层。

公开(公告)号：US20190043983A1

公开(公告)日：2019-02-07

申请号：US16028146

申请日：2018-07-05

Applicant: Renesas Electronics Corporation

Inventor： Taro MORIYA ,  Hiroyoshi KUDOU ,  Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/763 ,  H01L27/06 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, and a first contact plug. The semiconductor substrate includes a first surface and a second surface. Over the semiconductor substrate, a source region, a drain region, a drift region, and a body region are formed. A first trench in which the gate electrode is buried is formed in the first surface. The first surface includes an effective region and a peripheral region. The first trench extends from the peripheral region over the effective region along a first direction. The gate electrode includes a portion opposed to and insulated from the body region sandwiched between the source region and the drift region. In the peripheral region, the first contact plug is electrically coupled to the gate electrode buried in the first trench such that its longer side is along the first direction when seen in a plan view.

公开(公告)号：US20170263753A1

公开(公告)日：2017-09-14

申请号：US15401095

申请日：2017-01-08

Applicant: Renesas Electronics Corporation

Inventor： Taro MORIYA ,  Hiroyoshi KUDOU ,  Satoshi UCHIYA

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/768 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L29/7813 ,  H01L21/76897 ,  H01L23/5283 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7811

Abstract: To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region.

公开(公告)号：US20140322877A1

公开(公告)日：2014-10-30

申请号：US14324632

申请日：2014-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki KATOU ,  Taro MORIYA ,  Hiroyoshi KUDOU ,  Satoshi UCHIYA

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L27/0629 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7827

Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

Abstract translation: 沟槽栅型MISFET和二极管形成在半导体衬底中。 第一和第二沟槽形成在半导体衬底中。 栅电极通过栅极绝缘膜形成在第一沟槽中。 虚拟栅电极通过虚拟栅极绝缘膜形成在第二沟槽中。 阴极n +型半导体区域和阳极p型半导体区域形成在半导体衬底中，并且第二沟槽形成为在平面图中包围n +型半导体区域。 阳极p型半导体区域的一部分直接形成在n +型半导体区域正下方，从而在阳极p型半导体区域和n +型半导体区域的部分之间形成PN结。 从而形成二极管。 虚拟栅电极电耦合到阳极和阴极之一。

公开(公告)号：US20210398969A1

公开(公告)日：2021-12-23

申请号：US17314457

申请日：2021-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyoshi KUDOU ,  Taro MORIYA ,  Satoshi UCHIYA

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device has a silicon film for a diode formed on a semiconductor substrate via an insulating film, and first and second wirings formed on an upper layer of the silicon film. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring.

公开(公告)号：US20170263755A1

公开(公告)日：2017-09-14

申请号：US15455410

申请日：2017-03-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyoshi KUDOU ,  Taro MORIYA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p−-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p−-type guard ring region.

公开(公告)号：US20140138774A1

公开(公告)日：2014-05-22

申请号：US14061355

申请日：2013-10-23

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki KATOU ,  Taro MORIYA ,  Satoshi UCHIYA ,  Hiroyoshi KUDOU

IPC: H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

Abstract translation: 半导体器件包括设置在第一导电类型的漏极区域上的第二导电类型的基极区域，设置成覆盖基极区域的外周端并且具有较低的杂质浓度的第二导电类型的外围阱区域 与基极区相比埋入半导体衬底中的不与外围阱区重叠的埋入电极，与埋入电极连接并埋设在基板中的多个栅极，使得它们各自与源极区相邻， 栅极互连设置在所述衬底上以在平面图中与所述外围周边阱区域的一部分重叠并连接到所述掩埋电极，以及接地电极，设置在所述衬底上并连接到所述外部周边阱区域的不与所述栅极重叠的部分 在平面图中互连。