公开(公告)号：US20210159331A1

公开(公告)日：2021-05-27

申请号：US17095241

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Satoru TOKUDA ,  Ryuuji UMEMOTO ,  Katsumi EIKYU ,  Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

公开(公告)号：US20230118274A1

公开(公告)日：2023-04-20

申请号：US17887156

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Katsumi EIKYU ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.

公开(公告)号：US20160043214A1

公开(公告)日：2016-02-11

申请号：US14918966

申请日：2015-10-21

Applicant: Renesas Electronics Corporation

Inventor： Satoru TOKUDA

IPC: H01L29/78

CPC classification number: H01L29/7811 ,  H01L21/3065 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ≧90% and ≦110% of the depth of the first concave portion. The thickness of LIL2 is ≧95% and ≦105% of the thickness of LIL1. The UIF is thicker than the GIF.

Abstract translation: 第一下绝缘膜（LIL1）形成在第一凹部（栅极沟槽）的下表面和侧面的下部，并且比栅极绝缘膜（GIF）厚。 LIL1的上端连接到GIF的下端。 第二下绝缘膜形成在第二凹部（端接沟槽）的底表面和侧表面的下部。 上绝缘膜（UIF）形成在第二凹部的侧面的上部，下端与LIL2的上端连接。 第二凹部的深度为第一凹部的深度的90％以上且110％以下。 LIL2的厚度为≥95％，＆llE; LIL1厚度的105％。 UIF比GIF厚。

公开(公告)号：US20240088238A1

公开(公告)日：2024-03-14

申请号：US18330660

申请日：2023-06-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoru TOKUDA

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L29/407 ,  H01L29/7813

Abstract: A semiconductor device includes a trench formed in an n-type semiconductor substrate, a p-type body region, an n-type source region, a field plate electrode formed at a lower portion of the trench, and a gate electrode formed at an upper portion of the trench. A gate potential is to be supplied to the gate electrode, a source potential is to be supplied to the source region and the body region, and a drain potential is to be supplied to the semiconductor substrate. A potential larger than the source potential and smaller than the drain potential is to be supplied to the field plate electrode.

公开(公告)号：US20230111142A1

公开(公告)日：2023-04-13

申请号：US17886049

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Yuta NABUCHI ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.

公开(公告)号：US20180366575A1

公开(公告)日：2018-12-20

申请号：US15956611

申请日：2018-04-18

Applicant: Renesas Electronics Corporation

Inventor： Hiroyoshi KUDOU ,  Satoru TOKUDA ,  Satoshi UCHIYA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L23/4824 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7803

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.

公开(公告)号：US20200258979A1

公开(公告)日：2020-08-13

申请号：US16782802

申请日：2020-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoru TOKUDA

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device that achieves both miniaturization and high breakdown voltage is disclosed. The semiconductor device has a gate electrode G1 formed in a trench TR extending in Y direction and a plurality of column regions PC including column regions PC1 to PC3 formed in a drift region ND. The column regions PC1, PC2 and PC3 are provided in a staggered manner to sandwich the trench TR. An angle θ1 formed by a line connecting the centers of the column regions PC1 and PC2 and a line connecting the centers of the column regions PC1 and PC3 is 60 degrees or more and 90 degrees or less.

公开(公告)号：US20200020799A1

公开(公告)日：2020-01-16

申请号：US16446044

申请日：2019-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki UEDA ,  Satoru TOKUDA ,  Satoshi UCHIYA ,  Hiroyoshi KUDOU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device capable of reducing the influence of noise and easily securing a breakdown voltage between a source wiring and a drain wiring constituting a capacitance between a source and a drain even when shrinkage of a cell progresses, and a manufacturing method thereof are provided. The drain wiring is electrically connected to a substrate region, and the drain wiring is disposed in contact with an upper surface of an interlayer insulating layer. The source wiring is electrically connected to source regions and are disposed in contact with the upper surface of the interlayer insulating layer. A plurality of MOSFET cells are arranged side by side in a X-direction. The drain wiring and the source wiring extends in the X direction and are adjacent to each other in a Y direction crossing the X direction to form a capacitor.

公开(公告)号：US20180138311A1

公开(公告)日：2018-05-17

申请号：US15723662

申请日：2017-10-03

Applicant: Renesas Electronics Corporation

Inventor： Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L29/7813 ,  H01L21/76802 ,  H01L21/7688 ,  H01L21/76895 ,  H01L23/4824 ,  H01L23/535 ,  H01L29/66734

Abstract: The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area.The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.

公开(公告)号：US20140210000A1

公开(公告)日：2014-07-31

申请号：US14152233

申请日：2014-01-10

Applicant: Renesas Electronics Corporation

Inventor： Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L21/3065 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ≧90% and ≦110% of the depth of the first concave portion. The thickness of LIL2 is ≧95% and ≦105% of the thickness of LIL1. The UIF is thicker than the GIF.

Abstract translation: 第一下绝缘膜（LIL1）形成在第一凹部（栅极沟槽）的下表面和侧面的下部，并且比栅极绝缘膜（GIF）厚。 LIL1的上端连接到GIF的下端。 第二下绝缘膜形成在第二凹部（端接沟槽）的底表面和侧表面的下部。 上绝缘膜（UIF）形成在第二凹部的侧面的上部，下端与LIL2的上端连接。 第二凹部的深度为第一凹部的深度的90％以上且110％以下。 LIL2的厚度为≥95％，＆llE; LIL1厚度的105％。 UIF比GIF厚。