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    Semiconductor apparatus
    1.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US09293456B2

    公开(公告)日：2016-03-22

    申请号：US14508771

    申请日：2014-10-07

    Applicant: Renesas Electronics Corporation

    Inventor： Junichi Nita ,  Kazutaka Suzuki ,  Takahiro Korenari ,  Yoshimasa Uchinuma

    IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08

    CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0865 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.

    Abstract translation: 根据一个实施例，半导体装置将其中形成有第一晶体管的第一区域和其中形成第二晶体管的第二区域分成两个或更多个区域，并且交替地布置第一区域和 第二区。 此外，根据一个实施例的半导体装置将第二区域配置成具有比第一区域大的区域，或者具有大于第一区域的分割数量的区域的总面积。 此外，在根据一个实施例的半导体装置中，第二晶体管的栅极焊盘和第二晶体管的栅极焊盘设置在第二区域中。

    Sense MOSFET electrically connected to a source pad via a plurality of source extraction ports
    3.
    发明授权
    Sense MOSFET electrically connected to a source pad via a plurality of source extraction ports 有权

    公开(公告)号：US11373941B2

    公开(公告)日：2022-06-28

    申请号：US17068446

    申请日：2020-10-12

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yoshimasa Uchinuma ,  Yusuke Ojima

    IPC: H01L23/495 ,  H01L23/48 ,  H01L21/00 ,  H05K7/18 ,  H01L23/31 ,  H01L27/088 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.

    SEMICONDUCTOR APPARATUS
    5.
    发明申请
    SEMICONDUCTOR APPARATUS 有权

    公开(公告)号：US20150129958A1

    公开(公告)日：2015-05-14

    申请号：US14508771

    申请日：2014-10-07

    Applicant: Renesas Electronics Corporation

    Inventor： Junichi Nita ,  Kazutaka Suzuki ,  Takahiro Korenari ,  Yoshimasa Uchinuma

    IPC: H01L27/088 ,  H01L21/768

    CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0865 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.

    Abstract translation: 根据一个实施例，半导体装置将其中形成有第一晶体管的第一区域和其中形成第二晶体管的第二区域分成两个或更多个区域，并且交替地布置第一区域和 第二区。 此外，根据一个实施例的半导体装置将第二区域配置成具有比第一区域大的区域，或者具有大于第一区域的分割数量的区域的总面积。 此外，在根据一个实施例的半导体装置中，第二晶体管的栅极焊盘和第二晶体管的栅极焊盘设置在第二区域中。

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