公开(公告)号：US09536803B2

公开(公告)日：2017-01-03

申请号：US14847558

申请日：2015-09-08

Applicant: RF Micro Devices, Inc.

Inventor： David Charles Sheridan ,  Robert Charles Dry ,  Don Willis

IPC: H01L23/34 ,  H01L25/07 ,  H05K7/20 ,  H01L27/095 ,  H01L27/088 ,  H01L29/10 ,  H01L23/373 ,  H01L23/367 ,  H01L23/498 ,  H01L29/423

CPC classification number: H01L23/345 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/49844 ,  H01L25/072 ,  H01L27/088 ,  H01L27/095 ,  H01L29/1079 ,  H01L29/4232 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K7/205 ,  H05K7/20963 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

Abstract translation: 具有耗尽型器件和增强型器件的集成电源模块被配置为在栅极信号丢失期间防止耗尽型器件的意外导通状态。 特别地，所公开的集成功率模块被构造成提供改进的隔离和导热性。 该结构包括具有用于耗尽型器件的底部漏极焊盘的衬底，其设置在衬底上，以及增强模式器件占位面积尺寸的空腔，其延伸穿过衬底到底部漏极焊盘。 导热和电绝缘的芯块基本上填充空腔，以在增强模式器件和用于耗尽型器件的底部漏极焊盘之间提供更高效的热路径。

公开(公告)号：US20160071781A1

公开(公告)日：2016-03-10

申请号：US14847558

申请日：2015-09-08

Applicant: RF Micro Devices, Inc.

Inventor： David Charles Sheridan ,  Robert Charles Dry ,  Don Willis

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/07 ,  H01L23/498

CPC classification number: H01L23/345 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/49844 ,  H01L25/072 ,  H01L27/088 ,  H01L27/095 ,  H01L29/1079 ,  H01L29/4232 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K7/205 ,  H05K7/20963 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

Abstract translation: 具有耗尽型器件和增强型器件的集成电源模块被配置为在栅极信号丢失期间防止耗尽型器件的意外导通状态。 特别地，所公开的集成功率模块被构造成提供改进的隔离和导热性。 该结构包括具有用于耗尽型器件的底部漏极焊盘的衬底，其设置在衬底上，以及增强模式器件占位面积尺寸的空腔，其延伸穿过衬底到底部漏极焊盘。 导热和电绝缘的芯块基本上填充空腔，以在增强模式器件和用于耗尽型器件的底部漏极焊盘之间提供更高效的热路径。

公开(公告)号：US09673312B2

公开(公告)日：2017-06-06

申请号：US14831428

申请日：2015-08-20

Applicant: RF Micro Devices, Inc.

Inventor： David Charles Sheridan ,  Xing Huang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/16 ,  H01L21/8236 ,  H03K17/082

CPC classification number: H01L29/78 ,  H01L21/8236 ,  H01L27/0883 ,  H01L29/16 ,  H03K17/0822

Abstract: A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current.

公开(公告)号：US20160056151A1

公开(公告)日：2016-02-25

申请号：US14831428

申请日：2015-08-20

Applicant: RF Micro Devices, Inc.

Inventor： David Charles Sheridan ,  Xing Huang

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/778 ,  H01L29/20 ,  H01L29/16

CPC classification number: H01L29/78 ,  H01L21/8236 ,  H01L27/0883 ,  H01L29/16 ,  H03K17/0822

Abstract: A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current.

Abstract translation: 功率半导体器件具有与上部晶体管共栅共享的上部晶体管和下部晶体管。 上部晶体管包括上部漏极，上部栅极和上部源极。 下部晶体管包括耦合到上部源极的下部漏极，下部栅极和耦合到上部栅极的下部源极。 上部晶体管是耗尽型器件，具有第一饱和电流。 下部晶体管是增强型器件，并且具有低于第一饱和电流的第二饱和电流。