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公开(公告)号:US20150201515A1
公开(公告)日:2015-07-16
申请号:US14595615
申请日:2015-01-13
Applicant: RF Micro Devices, Inc.
Inventor: Donald Joseph Leahy , Jungwoo Lee , John August Orlowski , Howard Joseph Holyoak
CPC classification number: H01L23/49811 , H01L21/4857 , H01L23/145 , H01L23/49822 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L2224/16238 , H01L2224/32225 , H01L2224/48091 , H01L2224/48229 , H01L2224/73265 , H01L2224/81444 , H01L2224/85444 , H01L2224/8592 , H01L2924/00014 , H01L2924/1421 , H01L2924/181 , H05K1/09 , H05K3/244 , H05K3/284 , H05K3/3436 , H05K2201/0338 , H05K2201/10674 , H05K2203/049 , H05K2203/1316 , Y10T29/49162 , H01L2224/48227 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
Abstract: An electronics module includes a non-conductive body, a first set of conductive features exposed on a surface of the non-conductive body, and a second set of conductive features exposed on the surface of the non-conductive body. The first set of conductive features is configured to connect to a wire bond component. The second set of conductive features is configured to connect to a flip chip component. A protective finish is provided over each one of the first set of conductive features and the second set of conductive features. The protective finish includes a layer of nickel less than 1 μm thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium.
Abstract translation: 电子模块包括非导电体,暴露在非导电体的表面上的第一组导电特征,以及暴露在非导电体的表面上的第二组导电特征。 第一组导电特征被配置成连接到引线接合部件。 第二组导电特征被配置为连接到倒装芯片部件。 在第一组导电特征和第二组导电特征中的每一个上提供保护整理。 保护层包括一层厚度小于1μm的镍层,镍层上的一层钯层和钯层上的一层金。