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公开(公告)号:US12132005B2
公开(公告)日:2024-10-29
申请号:US18507176
申请日:2023-11-13
IPC分类号: H01L23/544 , H01L23/14 , H01L23/32 , H01L25/065
CPC分类号: H01L23/544 , H01L23/145 , H01L23/32 , H01L25/0655
摘要: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
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公开(公告)号:US20240339376A1
公开(公告)日:2024-10-10
申请号:US18403864
申请日:2024-01-04
发明人: Seunghyun CHO , Eunho CHO
IPC分类号: H01L23/373 , H01L21/48 , H01L23/00 , H01L23/498
CPC分类号: H01L23/373 , H01L21/481 , H01L23/4985 , H01L24/16 , H01L24/32 , H01L24/73 , H01L23/145 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
摘要: A chip on film package includes a flexible base film having a first surface and a second surface opposite to the first surface, the base film having a chip mounting region on the first surface; a plurality of wirings extending from the chip mounting region on the first surface of the base film in a first direction parallel to an extending direction of the base film; a semiconductor chip mounted on the chip mounting region on the first surface of the base film and electrically connected to the plurality of wirings; a heat dissipation layer provided to have a predetermined thickness in a depth direction from the second surface of the base film in an area overlapping the chip mounting region, the heat dissipation layer including a laser-induced carbon material; and an insulating layer covering the heat dissipation layer on the second surface of the base film.
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公开(公告)号:US20240321762A1
公开(公告)日:2024-09-26
申请号:US18678813
申请日:2024-05-30
申请人: Intel Corporation
发明人: Mihir K. Roy , Stefanie M. Lotz , Wei-Lun Kane Jen
IPC分类号: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H05K1/03 , H05K1/14 , H05K1/18 , H05K3/34 , H05K3/46
CPC分类号: H01L23/5386 , H01L21/4853 , H01L23/13 , H01L23/145 , H01L23/49811 , H01L23/49866 , H01L23/49894 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H05K1/141 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81193 , H01L2224/81203 , H01L2924/0002 , H01L2924/0665 , H01L2924/12042 , H01L2924/15192 , H01L2924/1579 , H01L2924/2064 , H05K1/0313 , H05K1/142 , H05K1/181 , H05K3/3436 , H05K3/467 , H05K2201/048 , H05K2201/049 , H05K2201/10522 , H05K2201/10674 , H05K2203/016
摘要: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
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公开(公告)号:US12091510B2
公开(公告)日:2024-09-17
申请号:US16764831
申请日:2019-04-09
申请人: LG CHEM, LTD.
发明人: Changbo Shim , Hyunsung Min , Hee Yong Shim , Hwayeon Moon , Seunghyun Song
IPC分类号: C08G59/56 , B32B5/26 , B32B7/027 , B32B7/12 , B32B15/08 , B32B15/14 , B32B15/20 , B32B27/38 , C08G59/68 , C08G73/12 , C08J5/24 , C08K3/36 , C08K5/5419 , C08K5/544 , C08K9/06 , C08L33/08 , C08L63/00 , C08L79/08 , H01L23/00 , H01L23/14 , H05K1/02 , H05K1/03
CPC分类号: C08G73/12 , B32B5/26 , B32B7/027 , B32B7/12 , B32B15/08 , B32B15/14 , B32B15/20 , B32B27/38 , C08G59/56 , C08G59/686 , C08J5/244 , C08J5/249 , C08K3/36 , C08K5/5419 , C08K9/06 , C08L33/08 , C08L63/00 , C08L79/08 , H01L23/145 , H01L23/562 , H05K1/0271 , H05K1/0373 , B32B2250/40 , B32B2260/021 , B32B2260/023 , B32B2260/046 , B32B2262/101 , B32B2307/734 , B32B2457/00 , B32B2457/14 , C08J2363/00 , C08J2433/08 , C08J2479/08 , C08K2201/003 , C08K2201/014 , C08L2205/025 , C08L2205/035 , H05K2201/068
摘要: The present disclosure relates to a thermosetting resin composite having a specific thermal stress factor, and capable of implementing a low glass transition temperature, low modulus, and a low coefficient of thermal expansion, and minimizing warpage, and having excellent flowability in a prepreg or semi-cured state, and a metal clad laminate using the same.
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公开(公告)号:US20240290725A1
公开(公告)日:2024-08-29
申请号:US18654143
申请日:2024-05-03
发明人: Wenqi ZHANG
CPC分类号: H01L23/5386 , H01L21/486 , H01L23/5384 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L23/145 , H01L23/147 , H01L23/3185 , H01L25/18 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125
摘要: A packaging structure includes: a first redistribution structure, where a distribution layer is disposed in the first redistribution structure; a plastic packaging structure, where the plastic packaging structure wraps a surface of the first redistribution structure other than an upper surface, and each of the at least one through via penetrates an upper surface and a lower surface of the plastic packaging structure; and a first chip and a second chip, where the first chip and the second chip are disposed above the first redistribution structure and the plastic packaging structure, the first chip is connected to the second chip by using the distribution layer, and at least a part of lead-out ends of the first chip and at least a part of lead-out ends of the second chip are led from the upper surface of the plastic packaging structure to the lower surface.
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公开(公告)号:US20240244833A1
公开(公告)日:2024-07-18
申请号:US18552837
申请日:2021-09-02
IPC分类号: H10B12/00 , H01L21/302 , H01L23/14 , H01L29/06
CPC分类号: H10B12/488 , H01L21/302 , H01L23/145 , H01L29/0653 , H10B12/02 , H10B12/482
摘要: A dynamic random access memory and a forming method therefor. The dynamic random access memory comprises: a substrate (100), which has opposite first surface (101) and second surface (102), and comprises several active regions (103), and each active region (103) comprises an isolation region (104), a channel region (105) and a word line region (106); a first isolation layer (108), which is located in the isolation region (104); a word line gate structure (111), which is located in the word line region (106); a first source/drain dope region (112), which is located in the channel region (105) on the first surface (101); a bit line layer (114) which is located on the first surface (101); a second source/drain dope region (116) which is located in the channel region (105) on the second surface (102); and several capacitor structures (119), which are located on the second surface (102).
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公开(公告)号:US12021015B2
公开(公告)日:2024-06-25
申请号:US16275957
申请日:2019-02-14
发明人: Hiroki Tamiya , Koji Kishino , Ryuji Takahashi , Yasunori Hoshino , Takahiro Yamada , Shimpei Obata , Hiroyuki Shiraki , Shinya Arakawa , Shigetoshi Fujita
IPC分类号: H01L23/498 , C08K9/04 , H01L23/14
CPC分类号: H01L23/49827 , C08K9/04 , H01L23/145 , C08L2203/20 , C08L2207/53 , H01L2224/16225 , C08K9/04 , C08L63/00
摘要: A thermosetting resin composition according to the invention contains: a thermosetting resin component; and silica having an average particle diameter equal to or greater than 0.2 μm and treated with isocyanate. It is preferable that the content of the silica is in a range of 50% by mass to 300% by mass with respect to the thermosetting resin component. It is also preferable that the thermosetting resin composition contains core shell rubber having content in a range of 20% by mass to 80% by mass with respect to the thermosetting resin component.
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公开(公告)号:US12014963B2
公开(公告)日:2024-06-18
申请号:US17362088
申请日:2021-06-29
发明人: Tomas Manuel Reiter , Peter Bayer , Christoph Koch
IPC分类号: H01L23/053 , H01L23/14 , H01L23/495 , H01L23/528 , H05K3/40 , H05K3/32
CPC分类号: H01L23/053 , H01L23/145 , H01L23/49503 , H01L23/5286 , H05K3/40 , H05K3/32
摘要: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions. Methods of producing the power semiconductor module and power electronic assemblies that incorporate the power semiconductor module are also described.
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公开(公告)号:US20240194493A1
公开(公告)日:2024-06-13
申请号:US18078049
申请日:2022-12-08
发明人: Yu-Hung YEH , Bing-Xiu LU , Yu Lin LU , Tai-Yuan HUANG
IPC分类号: H01L21/463 , H01L21/4763 , H01L21/66 , H01L23/14 , H01L23/544
CPC分类号: H01L21/463 , H01L21/47635 , H01L22/12 , H01L23/145 , H01L23/544
摘要: A substrate includes a dielectric structure, a conductive layer, a first hole and a second hole. The conductive layer is stacked on the dielectric structure. The first hole extends from a top surface of the conductive layer and exposes the dielectric structure. The second hole is spaced apart from the first hole, extends from the top surface of the conductive layer and exposes the dielectric structure. A first depth of the first hole is substantially equal to a second depth of the second hole. An elevation of a topmost end of the first hole is different from an elevation of a topmost end of the second hole.
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公开(公告)号:US20240186196A1
公开(公告)日:2024-06-06
申请号:US18442283
申请日:2024-02-15
申请人: ROHM CO., LTD.
发明人: Bungo TANAKA , Yuta KASHITANI , Toshiyuki KANAYA , Keiji WADA , Genki MATSUYAMA
IPC分类号: H01L23/14
CPC分类号: H01L23/145
摘要: An electronic component includes an underlay resin, and a pad electrode that has a sidewall located on the underlay resin and an uneven portion formed at a lower end portion of the sidewall.
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