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公开(公告)号:US20240347939A1
公开(公告)日:2024-10-17
申请号:US18632884
申请日:2024-04-11
Inventor: Wei (David) Zhao , Joshua Tyler Sechrist , Christopher Blackburn
CPC classification number: H01R12/714 , H05K1/181 , H05K3/3436 , H05K2201/10265 , H05K2201/1053 , H05K2201/10598
Abstract: An electronic assembly comprises a circuit board, a connector module, and a fixing assembly. The connector module includes a module housing and connection members at least partially accommodated therein. An engagement structure is formed on the module housing. The fixing assembly is adapted to be engaged with the engagement structure to secure the connector module to the circuit board, such that the connection members are electrically connected to the circuit board.
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公开(公告)号:US20240321762A1
公开(公告)日:2024-09-26
申请号:US18678813
申请日:2024-05-30
Applicant: Intel Corporation
Inventor: Mihir K. Roy , Stefanie M. Lotz , Wei-Lun Kane Jen
IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H05K1/03 , H05K1/14 , H05K1/18 , H05K3/34 , H05K3/46
CPC classification number: H01L23/5386 , H01L21/4853 , H01L23/13 , H01L23/145 , H01L23/49811 , H01L23/49866 , H01L23/49894 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H05K1/141 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81193 , H01L2224/81203 , H01L2924/0002 , H01L2924/0665 , H01L2924/12042 , H01L2924/15192 , H01L2924/1579 , H01L2924/2064 , H05K1/0313 , H05K1/142 , H05K1/181 , H05K3/3436 , H05K3/467 , H05K2201/048 , H05K2201/049 , H05K2201/10522 , H05K2201/10674 , H05K2203/016
Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
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公开(公告)号:US12089346B2
公开(公告)日:2024-09-10
申请号:US17742510
申请日:2022-05-12
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor: Hai-Tao Li , Hong-Hai Dai
CPC classification number: H05K3/361 , H05K1/0268 , H05K1/111 , H05K1/147 , H05K1/189 , H05K3/3426 , H05K3/3436 , H05K2201/056 , H05K2201/094
Abstract: A die package structure and a method for fabricating the same are provided. The method includes: fixing a first die on a package base; aligning first hollow pads of a flexible printed circuit board with first pads of the first die, and fixing the flexible printed circuit board; soldering the first hollow pads to the first pads; fixing a second die on the flexible printed circuit board to overlap with the first die; folding the flexible printed circuit board, such that second hollow pads of the flexible printed circuit board are aligned with second pads of the second die, and signal test pads of the flexible printed circuit board are exposed; fixing the flexible printed circuit board on the second die; soldering the second hollow pads to the second pads; soldering metal wires to the signal test soldering pads; and soldering package pins to the metal wires.
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公开(公告)号:US20240260237A1
公开(公告)日:2024-08-01
申请号:US18222776
申请日:2023-07-17
Applicant: Western Digital Technologies, Inc.
Inventor: Wei Hong Tew , Chun Sean Lau , Tze Ping Chan
CPC classification number: H05K7/205 , H05K1/0206 , H05K1/181 , H05K3/0052 , H05K7/20463 , H01L25/18 , H05K3/3436 , H05K2201/10159 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , H05K2201/10734 , H10B80/00
Abstract: A semiconductor storage device includes semiconductor packages mounted on a printed circuit board (PCB) and encased within an enclosure. The semiconductor storage device includes thermal interface material mounted on side edges of the PCB. During depaneling (separation) of individual semiconductor storage devices from a PCB panel, edges of the PCB may be overcut to expose thermally conductive edge layers provided within the interior the PCB. The thermal interface material may be positioned adjacent to the exposed thermally conductive edge layers to conduct heat away from a semiconductor package through the side edges of the PCB and out of sides of the enclosure.
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公开(公告)号:US12002762B2
公开(公告)日:2024-06-04
申请号:US16889190
申请日:2020-06-01
Applicant: Intel Corporation
Inventor: Mihir K Roy , Stefanie M Lotz , Wei-Lun Kane Jen
IPC: H01L23/00 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L23/538 , H01L25/065 , H05K1/14 , H05K1/03 , H05K1/18 , H05K3/34 , H05K3/46
CPC classification number: H01L23/5386 , H01L21/4853 , H01L23/13 , H01L23/145 , H01L23/49811 , H01L23/49866 , H01L23/49894 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H05K1/141 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81193 , H01L2224/81203 , H01L2924/0002 , H01L2924/0665 , H01L2924/12042 , H01L2924/15192 , H01L2924/1579 , H01L2924/2064 , H05K1/0313 , H05K1/142 , H05K1/181 , H05K3/3436 , H05K3/467 , H05K2201/048 , H05K2201/049 , H05K2201/10522 , H05K2201/10674 , H05K2203/016 , H01L2924/12042 , H01L2924/00
Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.
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公开(公告)号:US20240047325A1
公开(公告)日:2024-02-08
申请号:US18210157
申请日:2023-06-15
Applicant: REALTEK SEMICONDUCTOR CORP.
Inventor: CHIN-YUAN LO , HSIN-HUI LO
IPC: H01L23/498 , H05K3/34 , H01L23/00
CPC classification number: H01L23/49816 , H05K3/3436 , H01L24/16 , H01L2924/15311 , H01L2224/16225 , H05K2201/10734
Abstract: A ball grid array and a configuration method of the same are provided. The ball grid array is formed on a printed circuit board and includes an inner row region and an outer row region. The inner row region includes a plurality of first solder balls that are arranged by a first ball pitch. The first solder balls respectively correspond to a plurality of predetermined vias, and the first ball pitch is determined according to a minimum trace width that is relative to a via size of the predetermined vias. The outer row region surrounds the inner row region and includes a plurality of second solder balls that are arranged by a second ball pitch. The second ball pitch is smaller than the first ball pitch.
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公开(公告)号:US20230363085A1
公开(公告)日:2023-11-09
申请号:US17737333
申请日:2022-05-05
Applicant: NVIDIA Corp.
Inventor: MingYi Yu , Greg Bodi , Ananta Attaluri
CPC classification number: H05K1/0262 , H05K1/181 , H05K3/3436 , H01L23/36 , H01L23/49816 , H01L23/50 , H05K2201/10734 , H05K2201/10704
Abstract: A circuit system includes an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of connections on a shelf region extending beyond an area of the cutout.
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公开(公告)号:US20230354523A1
公开(公告)日:2023-11-02
申请号:US18220026
申请日:2023-07-10
Applicant: Amkor Technology Singapore Holding Pte. Ltd.
Inventor: Akito Yoshida , Mahmoud Dreiza , Curtis Michael Zwenger
IPC: H05K1/14 , H01L23/31 , H01L23/00 , H05K1/11 , H05K1/18 , H05K3/30 , H05K3/34 , H01L21/56 , H01L23/498 , H05K3/36 , H05K3/40
CPC classification number: H05K1/14 , H01L23/3128 , H01L24/10 , H05K1/11 , H05K1/181 , H05K1/184 , H05K3/303 , H05K3/34 , H01L21/56 , H01L23/3107 , H01L23/49811 , H01L24/16 , H01L24/81 , H05K1/185 , H05K3/363 , H05K3/4007 , Y10T29/49165 , H01L2224/1191 , H01L23/3171 , H05K3/3436 , H01L2224/13021 , H01L2224/13022 , H05K2201/10515 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/16111 , H05K2201/10977 , H05K2203/043 , H01L2224/16055 , H01L2224/1607 , H01L2224/16113 , H01L2224/16238 , H01L2224/81815 , H01L2924/01029 , H01L2924/01079
Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A
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公开(公告)号:US20230328895A1
公开(公告)日:2023-10-12
申请号:US18335383
申请日:2023-06-15
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Takashi KITAHARA , Kensuke OTAKE , Kyo SHIN
CPC classification number: H05K3/3436 , H05K3/3463 , H05K1/181
Abstract: The present disclosure is directed to an electronic component mounting structure including: a circuit board provided on a surface thereof with a first electrode containing Cu as a main component; and an electronic component mounted on the circuit board, the electronic component including a second electrode on a surface thereof; wherein the second electrode includes a first plating containing Ni as a main component and a second plating containing Sn as a main component formed on a surface of the first plating, and an intermediate bonding layer is provided between the first plating and the first electrode, and the intermediate bonding layer includes a first region containing an alloy of Cu and Sn as a main component and a second region containing Sn as a main component.
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公开(公告)号:US11735563B2
公开(公告)日:2023-08-22
申请号:US17512123
申请日:2021-10-27
Applicant: Invensas LLC
Inventor: Ellis Chau , Reynaldo Co , Roseann Alatorre , Philip Damberg , Wei-Shun Wang , Se Young Yang
IPC: H01L23/00 , H01L23/31 , H01L23/498 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/495 , H01L21/48 , H01L23/367 , H01L23/433 , H01L25/065 , H05K3/34
CPC classification number: H01L24/85 , H01L21/4853 , H01L21/56 , H01L23/3128 , H01L23/3677 , H01L23/4334 , H01L23/49517 , H01L23/49811 , H01L23/49816 , H01L24/06 , H01L24/43 , H01L24/78 , H01L25/105 , H01L25/50 , H01L21/565 , H01L23/3114 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/05599 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/4554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4824 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48245 , H01L2224/48247 , H01L2224/48997 , H01L2224/49171 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/78301 , H01L2224/851 , H01L2224/8518 , H01L2224/85399 , H01L2224/85951 , H01L2224/85986 , H01L2225/0651 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06558 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1029 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2225/1094 , H01L2924/00011 , H01L2924/00012 , H01L2924/00014 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/1715 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/3511 , H05K3/3436 , H05K2201/1053 , H05K2201/10515 , Y10T29/49149 , Y10T29/49151 , H01L2224/45565 , H01L2224/45147 , H01L2224/45664 , H01L2224/45565 , H01L2224/45144 , H01L2224/45664 , H01L2924/19107 , H01L2224/45144 , H01L2224/45565 , H01L2224/45664 , H01L2924/19107 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/78301 , H01L2924/00014 , H01L2224/85986 , H01L2224/8518 , H01L2224/85951 , H01L2224/49171 , H01L2224/48227 , H01L2924/00 , H01L2224/49171 , H01L2224/48247 , H01L2924/00 , H01L2224/4824 , H01L2224/49171 , H01L2924/00 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32145 , H01L2224/48145 , H01L2924/00012 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2924/00012 , H01L2224/45144 , H01L2924/00 , H01L2224/45124 , H01L2924/00 , H01L2224/45147 , H01L2924/00 , H01L2224/73265 , H01L2224/32145 , H01L2224/48247 , H01L2924/00 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00 , H01L2224/73265 , H01L2224/32245 , H01L2224/48227 , H01L2924/00 , H01L2224/73265 , H01L2224/32225 , H01L2224/48247 , H01L2924/00 , H01L2224/73204 , H01L2224/16145 , H01L2224/32145 , H01L2924/00 , H01L2224/131 , H01L2924/014 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/15311 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00 , H01L2924/01047 , H01L2924/00 , H01L2224/48091 , H01L2924/00014 , H01L2224/45015 , H01L2924/00 , H01L2224/45144 , H01L2924/00014 , H01L2224/45147 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/20751 , H01L2224/45015 , H01L2924/20752 , H01L2224/45015 , H01L2924/20753 , H01L2224/45015 , H01L2924/20754 , H01L2224/45015 , H01L2924/20755 , H01L2224/45015 , H01L2924/20756 , H01L2224/45015 , H01L2924/20757 , H01L2224/45015 , H01L2924/20758 , H01L2224/45015 , H01L2924/20759 , H01L2224/45015 , H01L2924/2076 , H01L2224/85399 , H01L2924/00014 , H01L2224/05599 , H01L2924/00014 , H01L2924/00011 , H01L2924/01049
Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
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