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    State detection circuit for detecting tri-state and state detection method thereof
    1.
    发明授权
    State detection circuit for detecting tri-state and state detection method thereof 有权

    公开(公告)号：US12111339B2

    公开(公告)日：2024-10-08

    申请号：US18050928

    申请日：2022-10-28

    Applicant: Richtek Technology Corporation

    Inventor： Chun-Jen Yu ,  Hsuan-Kai Wang ,  Chi-Jen Yang ,  Hsien-Chih She

    IPC: G01R19/165 ,  G01R31/317

    CPC classification number: G01R19/1659 ,  G01R31/317

    Abstract: A state detection circuit for detecting whether a state of an input node is floating, grounded, or electrically connected to an external voltage includes: a unidirectional device circuit and a determination circuit. The unidirectional device circuit electrically conducts a test node to a detection node unidirectionally. The detection node is coupled to the input node. The test node, the unidirectional device circuit, the detection node and the input node form a current path. The determination circuit determines a state of the input node according to a voltage level of the detection node. Within a detection stage, the state detection circuit provides a test voltage at the test node. A voltage of the detection node is determined by the input node, the test voltage, and a characteristic of the unidirectional device circuit.

    STATE DETECTION CIRCUIT FOR DETECTING TRI-STATE AND STATE DETECTION METHOD THEREOF
    2.
    发明公开
    STATE DETECTION CIRCUIT FOR DETECTING TRI-STATE AND STATE DETECTION METHOD THEREOF 审中-公开

    公开(公告)号：US20230160935A1

    公开(公告)日：2023-05-25

    申请号：US18050928

    申请日：2022-10-28

    Applicant: Richtek Technology Corporation

    Inventor： Chun-Jen Yu ,  Hsuan-Kai Wang ,  Chi-Jen Yang ,  Hsien-Chih She

    IPC: G01R19/165 ,  G01R31/317

    CPC classification number: G01R19/1659 ,  G01R31/317

    Abstract: A state detection circuit for detecting whether a state of an input node is floating, grounded, or electrically connected to an external voltage includes: a unidirectional device circuit and a determination circuit. The unidirectional device circuit electrically conducts a test node to a detection node unidirectionally. The detection node is coupled to the input node. The test node, the unidirectional device circuit, the detection node and the input node form a current path. The determination circuit determines a state of the input node according to a voltage level of the detection node. Within a detection stage, the state detection circuit provides a test voltage at the test node. A voltage of the detection node is determined by the input node, the test voltage, and a characteristic of the unidirectional device circuit.

    AMPLIFIER CIRCUIT HAVING LOW PARASITIC POLE EFFECT AND BUFFER CIRCUIT THEREOF
    3.
    发明公开
    AMPLIFIER CIRCUIT HAVING LOW PARASITIC POLE EFFECT AND BUFFER CIRCUIT THEREOF 审中-公开

    公开(公告)号：US20230198473A1

    公开(公告)日：2023-06-22

    申请号：US18056329

    申请日：2022-11-17

    Applicant: Richtek Technology Corporation

    Inventor： Chun-Jen Yu ,  Ssu-Wei Huang ,  Hsuan-Kai Wang ,  Chi-Jen Yang ,  Hsien-Chih She

    IPC: H03F1/14 ,  H03F1/42

    CPC classification number: H03F1/14 ,  H03F1/42 ,  H03F2200/222

    Abstract: An amplifier circuit having low parasitic pole effect includes a preamplifier, an output transistor and a buffer circuit. The buffer circuit generates a driving signal to control the output transistor according to a preamplification signal generated by the preamplifier. The buffer circuit includes: a buffer input transistor generating the driving signal, wherein an input impedance at its control end is less than that of the output transistor; a low output impedance circuit having an output impedance which is less than an inverting output impedance of the buffer input transistor; an amplification transistor generating an amplification signal at its inverting output; and an amplification stage circuit amplifying the amplification signal by an amplification ratio, so that an equivalent output impedance at a non-inverting output of the buffer input transistor is less than or equal to a product of the reciprocal of an intrinsic output impedance thereof and an amplification ratio.

    CHARGER CIRCUIT AND CHARGING CONTROL METHOD
    4.
    发明申请
    CHARGER CIRCUIT AND CHARGING CONTROL METHOD 有权

    公开(公告)号：US20230070676A1

    公开(公告)日：2023-03-09

    申请号：US17840556

    申请日：2022-06-14

    Applicant: Richtek Technology Corporation

    Inventor： Hsuan-Kai Wang ,  Hsien-Chih She ,  Po-Cheng Liu

    IPC: H02J7/00 ,  H02J7/04 ,  G01R31/3835

    Abstract: A charger circuit includes: a power stage circuit configured to operate at least one power switch according to an operation signal, so as to convert an input power to a charging power to charge a battery; a control circuit coupled to the power stage circuit and configured to generate the operation signal according to a current feedback signal and a voltage feedback signal; a voltage feedback circuit configured to compare a voltage sensing signal related to a charging voltage of the charging power with a voltage reference level, so as to generate the voltage feedback signal; a battery core voltage drop sensing circuit coupled to a battery core of the battery and configured to sense a battery core voltage drop of the battery core, so as to generate a battery core voltage drop sensing signal; and an adjustment circuit coupled to the battery core voltage drop sensing circuit and configured to generate an adjustment signal according to the battery core voltage drop sensing signal, so as to adaptively adjust the voltage reference level.

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