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    Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream
    1.
    发明授权
    Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream 有权
    方法和系统，用于使用相同的寄存器组来处理指令流中的单精度和双精度浮点指令

    公开(公告)号：US07191316B2

    公开(公告)日：2007-03-13

    申请号：US10353662

    申请日：2003-01-29

    申请人： Rabin A. Sugumar ,  Sorin Iacobovici ,  Robert Nuckolls ,  Chandra M. R. Thimmannagari

    发明人： Rabin A. Sugumar ,  Sorin Iacobovici ,  Robert Nuckolls ,  Chandra M. R. Thimmannagari

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3836 ,  G06F9/30014 ,  G06F9/30101 ,  G06F9/384 ,  G06F9/3857

    摘要： A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

    摘要翻译： 提供了一种用于处理多个单精度浮点指令和多个双精度浮点指令的系统，它们都对同一组寄存器进行索引。 该系统包括解码单元，其被配置为在取出组中解码，停止和转发多个单精度和至少一个双精度浮点指令中的至少一个。 所述解码单元包括第一计数器，所述第一计数器被布置为针对沿管线转发的所述多个单精度浮点指令中的每一者递增; 第二计数器，被布置为针对沿着流水线转发的多个双精度浮点指令中的每一个递增; 第一屏蔽寄存器和第二掩码寄存器。 通过转发的每个单精度浮点指令来更新第一个掩码寄存器，并且通过转发的每个双精度浮点指令更新第二个掩码寄存器。

    Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor
    4.
    发明授权
    Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor 有权
    用于处理无序多问题多链处理器中条件码修改器的方法

    公开(公告)号：US07065635B1

    公开(公告)日：2006-06-20

    申请号：US10738576

    申请日：2003-12-17

    申请人： Rabin A. Sugumar ,  Sorin Iacobovici ,  Chandra M. R. Thimmannagari

    发明人： Rabin A. Sugumar ,  Sorin Iacobovici ,  Chandra M. R. Thimmannagari

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3842 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

    摘要： A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.

    摘要翻译： 一种用于处理无序多股处理器中的条件代码修改指令的技术包括为每条链提供条件代码体系结构寄存器文件，提供条件代码工作寄存器文件，以及分配条件码架构寄存器文件识别信息（ CARF_ID）和条件代码工作寄存器文件识别信息（CWRF_ID）到条件代码修改指令。 CARF_ID用于索引存储CWRF_ID的条件代码重命名表中的位置。 此后，在条件代码修改指令的无异常执行时，执行结果从条件代码工作寄存器文件复制到依赖于CARF_ID，CWRF_ID，寄存器类型信息和链标识信息的条件代码架构寄存器文件 。

    Branch prediction structure with branch direction entries that share branch prediction qualifier entries
    5.
    发明授权
    Branch prediction structure with branch direction entries that share branch prediction qualifier entries 有权
    具有共享分支预测限定符条目的分支方向条目的分支预测结构

    公开(公告)号：US07380110B1

    公开(公告)日：2008-05-27

    申请号：US10660169

    申请日：2003-09-11

    申请人： Robert D. Nuckolls ,  Rabin A. Sugumar ,  Chandra M. R. Thimmannagari

    发明人： Robert D. Nuckolls ,  Rabin A. Sugumar ,  Chandra M. R. Thimmannagari

    IPC分类号： G06F9/40 ,  G06F9/44

    CPC分类号： G06F9/3848

    摘要： An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst multiple entries of the first portion. In this way, overall storage (and layout area) can be reduced and scaling with a branch prediction structure that includes a (2N)K×1 branch direction entries and a (N/2)K×1 branch prediction qualifier entries is less dramatic than conventional techniques. An efficient branch prediction structure includes entries for branch direction indications and entries for branch prediction qualifier indications. The branch direction indication entries are more numerous than the branch prediction qualifier entries. An entry from the branch direction entries is selected based at least in part on a corresponding instruction instance identifier and an entry from the branch prediction qualifier entries is selected based at least in part on least significant bits of the instruction instance identifier.

    摘要翻译： 描述了一种有效的分支预测结构，其将分支预测结构分成至少两个部分，其中存储在第二部分中的信息在第一部分的多个条目之中进行混叠。 以这种方式，可以减少总体存储（和布局面积），并且使用包括（2N）Kx1分支方向条目和（N / 2）Kx1分支预测限定符条目的分支预测结构进行缩放比常规技术更不显着。 有效的分支预测结构包括用于分支方向指示的条目和用于分支预测限定符指示的条目。 分支方向指示条目比分支预测限定符条目更多。 至少部分地基于对应的指令实例标识符来选择来自分支方向条目的条目，并且至少部分地基于指令实例标识符的最低有效位来选择来自分支预测限定符条目的条目。

    Handling register dependencies between instructions specifying different width registers
    6.
    发明授权
    Handling register dependencies between instructions specifying different width registers 有权
    在指定不同宽度寄存器的指令之间处理寄存器依赖关系

    公开(公告)号：US07340590B1

    公开(公告)日：2008-03-04

    申请号：US10734763

    申请日：2003-12-11

    申请人： Rabin Sugumar ,  Sorin Iacobovici ,  Chandra M. R. Thimmannagari

    发明人： Rabin Sugumar ,  Sorin Iacobovici ,  Chandra M. R. Thimmannagari

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3836 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3017 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer instruction and a lesser width consumer instruction, a greater width source register is substituted for the source register specified by the lesser width producer. If there is a register dependency between a lesser width producer instruction and a greater width producer instruction, the greater width consumer instruction is replaced by multiple helper instructions. One or more of the helper instructions merge lesser width registers aliased onto the source registers specified by the greater width consumer instruction, into temporary registers. Another helper instruction executes the greater width consumer instruction using the temporary registers instead of the original source registers.

    摘要翻译： 本申请描述了一种用于处理较小和较大宽度指令之间的寄存器依赖性冲突的方法和处理器，通俗地称为“邪恶的双胞胎”。 如果在较大宽度的生产者指令和较小宽度的使用者指令之间存在寄存器依赖关系，则较大的宽度源寄存器将替代较小宽度生产者指定的源寄存器。 如果较小宽度生成器指令和较大宽度生成器指令之间存在寄存器依赖关系，则较大宽度的消费者指令将被多个辅助指令替换。 一个或多个辅助指令将较小宽度寄存器的别名合并到由较大宽度的消费者指令指定的源寄存器中，并入临时寄存器。 另一个帮助指令使用临时寄存器而不是原始源寄存器来执行更大的宽度使用者指令。

    Vector technique for addressing helper instruction groups associated with complex instructions
    7.
    发明授权
    Vector technique for addressing helper instruction groups associated with complex instructions 有权
    用于寻址与复杂指令相关联的辅助指令组的向量技术

    公开(公告)号：US07219218B2

    公开(公告)日：2007-05-15

    申请号：US10403530

    申请日：2003-03-31

    申请人： Chandra M. R. Thimmannagari ,  Sorin Iacobovici ,  Rabin Sugumar

    发明人： Chandra M. R. Thimmannagari ,  Sorin Iacobovici ,  Rabin Sugumar

    IPC分类号： G06F9/26 ,  G06F9/40

    CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

    摘要翻译： 本申请描述了一种用于在减少处理器中执行所需的逻辑的同时执行指令的方法和系统。 指令（例如，原子，整数乘法，整数除法，整数寄存器移动，图形，浮点计算等）在执行之前扩展为辅助指令（例如，在整数，浮点，图形和存储单元或 类似）。 这些说明被视为复杂的说明。 复杂指令的功能在多个助手之间共享，因此通过执行表示复杂指令的助手，实现了复杂指令的功能。 将复杂指令扩展到辅助指令中减少了处理器中各种单元支持这些单独复杂指令所涉及的硬件和复杂性的量。

    Replacement algorithm for a replicated fully associative translation look-aside buffer
    8.
    发明授权
    Replacement algorithm for a replicated fully associative translation look-aside buffer 有权

    公开(公告)号：US06810473B2

    公开(公告)日：2004-10-26

    申请号：US10336708

    申请日：2003-01-06

    申请人： Chandra M. R. Thimmannagari

    发明人： Chandra M. R. Thimmannagari

    IPC分类号： G06F1210

    CPC分类号： G06F12/128

    摘要： A method and apparatus determines whether there is an invalid address translation entry in a first translation look-aside buffer. If there is an invalid address translation entry in the first translation look-aside buffer, an invalid address translation entry in the first translation look-aside buffer is replaced. If there is no invalid address translation entry in the first translation look-aside buffer, a method and apparatus determines whether there is an invalid address translation entry in a second translation look-aside buffer. If there is an invalid address translation entry in the second translation look-aside buffer, an invalid address translation entry in the second translation look-aside buffer is replaced.