公开(公告)号：US08098539B2

公开(公告)日：2012-01-17

申请号：US12547578

申请日：2009-08-26

申请人： Raghu Sankuratri ,  Michael Drop ,  Jian Mao

发明人： Raghu Sankuratri ,  Michael Drop ,  Jian Mao

IPC分类号： G11C8/00

CPC分类号： G06F13/1684

摘要： A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

摘要翻译： 描述了存储器结构。 在一个实施例中，存储器结构包括被配置为接收时钟信号并且经由单个地址/控制总线耦合到多个存储器模块的存储器控​​制器。 存储器控制器经由用于每个存储器模块的单独芯片选择信号耦合到多个存储器模块中的每一个。 存储器控制器根据时钟提供的定时以交错的方式将地址/控制总线上的命令发送到存储器模块。 在向一个存储器模块发出命令之后的等待期间，存储器控制器可以向不同的存储器模块发出命令。

公开(公告)号：US20110055617A1

公开(公告)日：2011-03-03

申请号：US12547578

申请日：2009-08-26

申请人： Raghu Sankuratri ,  Michael Drop ,  Jian Mao

发明人： Raghu Sankuratri ,  Michael Drop ,  Jian Mao

IPC分类号： G06F1/04 ,  G06F12/00

CPC分类号： G06F13/1684

摘要： A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

摘要翻译： 描述了存储器结构。 在一个实施例中，存储器结构包括被配置为接收时钟信号并且经由单个地址/控制总线耦合到多个存储器模块的存储器控​​制器。 存储器控制器经由用于每个存储器模块的单独芯片选择信号耦合到多个存储器模块中的每一个。 存储器控制器根据时钟提供的定时以交错的方式将地址/控制总线上的命令发送到存储器模块。 在向一个存储器模块发出命令之后的等待期间，存储器控制器可以向不同的存储器模块发出命令。

公开(公告)号：US07804735B2

公开(公告)日：2010-09-28

申请号：US12039908

申请日：2008-02-29

申请人： Jian Mao ,  Raghu Sankuratri

发明人： Jian Mao ,  Raghu Sankuratri

IPC分类号： G11C8/00

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

摘要翻译： 介绍了降低接口引脚要求的双通道存储架构的设备和方法。 一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中 第二时钟信号的极性与第一时钟信号相反。 提出了一种执行数据交易的方法。 该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据 基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

公开(公告)号：US08325525B2

公开(公告)日：2012-12-04

申请号：US12860441

申请日：2010-08-20

申请人： Jian Mao ,  Raghu Sankuratri

发明人： Jian Mao ,  Raghu Sankuratri

IPC分类号： G11C16/04

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

摘要翻译： 介绍了降低接口引脚要求的双通道存储架构的设备和方法。 一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中 第二时钟信号的极性与第一时钟信号相反。 提出了一种执行数据交易的方法。 该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据 基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

公开(公告)号：US20100318730A1

公开(公告)日：2010-12-16

申请号：US12860441

申请日：2010-08-20

申请人： Jian Mao ,  Raghu Sankuratri

发明人： Jian Mao ,  Raghu Sankuratri

IPC分类号： G06F12/00 ,  G06F1/04 ,  G06F12/02

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

摘要翻译： 介绍了降低接口引脚要求的双通道存储架构的设备和方法。 一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中 第二时钟信号的极性与第一时钟信号相反。 提出了一种执行数据交易的方法。 该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据 基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

公开(公告)号：US20090219779A1

公开(公告)日：2009-09-03

申请号：US12039908

申请日：2008-02-29

申请人： Jian Mao ,  Raghu Sankuratri

发明人： Jian Mao ,  Raghu Sankuratri

IPC分类号： G11C8/18

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

摘要翻译： 介绍了降低接口引脚要求的双通道存储架构的设备和方法。 一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中 第二时钟信号的极性与第一时钟信号相反。 提出了一种执行数据交易的方法。 该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据 基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

公开(公告)号：US20110279477A1

公开(公告)日：2011-11-17

申请号：US13106372

申请日：2011-05-12

申请人： Guishen Wang ,  Jian Mao ,  Duane Herberg ,  Kevin Dillon ,  Suzann R. Mouw ,  Paul H. McDowall

发明人： Guishen Wang ,  Jian Mao ,  Duane Herberg ,  Kevin Dillon ,  Suzann R. Mouw ,  Paul H. McDowall

IPC分类号： G09G5/00

CPC分类号： G06F19/321 ,  G06F19/328 ,  G09G2380/08 ,  G16H40/20 ,  G16H40/40

摘要： An image processing and handling system is provided for the efficient combination of image data from multiple sources and of different types. The system includes an image processing device having an electronic control unit (ECU) that receives a first set of image data from an image data provider such as a PACS server over a telecommunications network. The first set of image data includes image pixel data from a first image of a physical structure in a living being and may be obtained from a DICOM compatible file. The ECU is further configured to combine the first set of image data with a second set of image data to form a combined set of image data. The second and combined sets of image data may each include pixel data for second and combined images, respectively of the physical structure. The ECU is further configured to transmit the combined set of image data to a remote computing device over a second telecommunications network

摘要翻译： 提供了一种图像处理和处理系统，用于高效地组合来自多个来源和不同类型的图像数据。 该系统包括具有电子控制单元（ECU）的图像处理装置，其通过电信网络从诸如PACS服务器的图像数据提供者接收第一组图像数据。 第一组图像数据包括来自生物中的物理结构的第一图像的图像像素数据，并且可以从DICOM兼容文件获得。 ECU还被配置为将第一组图像数据与第二组图像数据组合以形成组合的图像数据集合。 图像数据的第二组合和组合可以分别包括用于物理结构的第二和组合图像的像素数据。 ECU还被配置为通过第二电信网络将组合的图像数据集发送到远程计算设备

公开(公告)号：US07802354B2

公开(公告)日：2010-09-28

申请号：US12039647

申请日：2008-02-28

申请人： Jian Mao ,  Jian Min Wang ,  Heng Liu ,  Anbo Wu

发明人： Jian Mao ,  Jian Min Wang ,  Heng Liu ,  Anbo Wu

IPC分类号： B23P17/00 ,  B23P21/00

CPC分类号： G01R33/3806 ,  G01R33/3802 ,  Y10T29/49826 ,  Y10T29/49885 ,  Y10T29/49904 ,  Y10T29/49947 ,  Y10T29/49948

摘要： A multi-layered support structure of an open magnetic resonance imaging (MRI) system, configured to provide high permeability to a magnetic flux from a source of a magnetic field, includes a first multi-layered support structure, a second multi-layered support structure and at least one third support structure, connecting the first multi-layered support structure and the second multi-layered structure.

摘要翻译： 开放磁共振成像（MRI）系统的多层支撑结构被配置为从磁场源提供磁通量的高磁导率，包括第一多层支撑结构，第二多层支撑结构 以及连接第一多层支撑结构和第二多层结构的至少一个第三支撑结构。

公开(公告)号：US20050206564A1

公开(公告)日：2005-09-22

申请号：US11071249

申请日：2005-03-04

申请人： Jian Mao ,  Oscar Somerlock

发明人： Jian Mao ,  Oscar Somerlock

IPC分类号： H01Q3/22 ,  H01Q3/26 ,  H04B7/06 ,  H04B7/08

CPC分类号： H01Q3/2605 ,  H01Q3/2682

摘要： An adaptive beam-forming system using hierarchical weight banks for antenna arrays in wireless communication systems is disclosed. The present invention can be applied for both reception and transmission beam-forming. The hierarchical weight banks contain weights that are pre-calculated based on pre-set beam look directions. By comparing measurements of chosen signal quality metrics for pre-set look directions, the best weights, and thus the best beam look direction, can be selected from the weight banks.

摘要翻译： 公开了一种在无线通信系统中使用用于天线阵列的分级加权块的自适应波束形成系统。 本发明可以应用于接收和传输波束形成。 层次权重库包含基于预设波束外观方向预先计算的权重。 通过比较所选信号质量度量对于预设外观方向的测量，可以从权重库中选择最佳权重，从而选择最佳波束查找方向。

公开(公告)号：US09142060B2

公开(公告)日：2015-09-22

申请号：US13599218

申请日：2012-08-30

申请人： Nariman Moezzi Madani ,  Jian Mao ,  Vineet Goel

发明人： Nariman Moezzi Madani ,  Jian Mao ,  Vineet Goel

IPC分类号： G06T17/20

CPC分类号： G06T17/20

摘要： Systems and methods for a tessellation are described. The tessellation unit is configured to determine a number of points that reside along a first edge of a first ring within a domain, determine a first set of coordinates for a first portion of the points that reside along the first edge of the first ring within the domain, and determine a second set of coordinates for a second portion of the points that reside along the first edge of the first ring within the domain based on the first set of coordinates for the first portion. The tessellation unit is also configured to stitch points that reside along the first edge of the first ring with points that reside along a second edge of a second ring to divide the domain into a plurality of primitives that are mapped to a patch.

摘要翻译： 描述了细分的系统和方法。 该细分单元被配置为确定沿着域内的第一环的第一边缘驻留的点的数量，确定沿着第一环的第一边缘驻留的点的第一部分的第一组坐标， 并且基于第一部分的第一坐标集合来确定沿着第一环的第一边缘的第一部分驻留的第二部分坐标的第二坐标集合。 细分单元还被配置为沿着沿着第二环的第二边缘驻留的点将沿着第一环的第一边缘的点进行缝合，以将该域划分成映射到补丁的多个基元。