公开(公告)号：US07298183B2

公开(公告)日：2007-11-20

申请号：US11142705

申请日：2005-06-01

Applicant: Ahmad Mirzaei ,  Mohammad E Heidari ,  Masoud Djafari ,  Rahim Bagheri

Inventor： Ahmad Mirzaei ,  Mohammad E Heidari ,  Masoud Djafari ,  Rahim Bagheri

IPC: H03K21/00

CPC classification number: H03K23/52 ,  H03K3/012 ,  H03K3/356 ,  H03K23/44

Abstract: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

Abstract translation: 本发明的实施例包括用于分割高频信号的电路和方法。 在一个实施例中，本发明包括一个分频器电路，包括具有第一和第二输入以接收第一差分信号的差分电路，第一频率控制输入和第一和第二差分输出，其中差分电路具有第一偏置电流。 除法器电路还包括具有耦合到差分电路输出和第二频率控制输入的输出的交叉耦合电路，其中交叉耦合电路具有第二偏置电流。 本发明的实施例可以包括用于控制偏置电流和随过程或温度变化的电路参数之间的关系或两者的电路。

公开(公告)号：US07941475B2

公开(公告)日：2011-05-10

申请号：US11501382

申请日：2006-08-09

Applicant: Rahim Bagheri ,  Ahmad Mirzaei

Inventor： Rahim Bagheri ,  Ahmad Mirzaei

IPC: G06G7/02

CPC classification number: H03H15/02

Abstract: Embodiments of the present invention include programmable filter circuits and methods. In one embodiment, the present invention includes a programmable filter for filtering an input signal comprising a storage element for storing a plurality of digital values representing a discrete time window function, and a plurality of filter channels, each channel comprising a multiplying digital-to-analog converter having a plurality of digital inputs coupled to the storage element and an analog input for receiving said input signal to be filtered, at least one capacitor having at least one terminal coupled to an output of the multiplying digital-to-analog converter, and a sampling device coupled between the at least one terminal of the at least one capacitor and an output of the filter. In another embodiment, the present invention includes a software defined radio.

Abstract translation: 本发明的实施例包括可编程滤波器电路和方法。 在一个实施例中，本发明包括一个可编程滤波器，用于对输入信号进行滤波，该输入信号包括用于存储表示离散时间窗函数的多个数字值的存储元件和多个滤波器通道，每个通道包括乘法数字 - 模拟转换器，其具有耦合到存储元件的多个数字输入端和用于接收要滤波的所述输入信号的模拟输入端，至少一个电容器，其至少一个端子耦合到乘法数模转换器的输出端，以及 耦合在所述至少一个电容器的所述至少一个端子和所述滤波器的输出端之间的采样装置。 在另一个实施例中，本发明包括软件定义的无线电装置。

公开(公告)号：US20070090877A1

公开(公告)日：2007-04-26

申请号：US11584453

申请日：2006-10-20

Applicant: Mahdi Bagheri ,  Rahim Bagheri ,  Ahmad Mirzaei ,  Abbas Komijani ,  Edris Rostami ,  Masoud Djafari

Inventor： Mahdi Bagheri ,  Rahim Bagheri ,  Ahmad Mirzaei ,  Abbas Komijani ,  Edris Rostami ,  Masoud Djafari

IPC: H03F3/45

CPC classification number: H03F1/48 ,  H03F3/191 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/168 ,  H03F2200/36 ,  H03F2203/45302 ,  H03F2203/45318 ,  H03F2203/45342 ,  H03F2203/45354

Abstract: Embodiments of the present invention include circuits and methods with wide bandwidths. In one embodiment, parasitic capacitances of the output of a first stage and the input of a second stage are included in a network. The output of the first stage is coupled to the input of the network, and the input of the second stage is coupled to an intermediate node of the network. In one embodiment, the parasitic capacitance of the second stage is the largest capacitance in the network. In another embodiment, passive networks are coupled to the outputs of a stage, and one or more current injection circuits may be used to extend the bandwidth of the circuit.

Abstract translation: 本发明的实施例包括具有宽带宽的电路和方法。 在一个实施例中，第一级的输出和第二级的输入的寄生电容包括在网络中。 第一级的输出耦合到网络的输入，并且第二级的输入耦合到网络的中间节点。 在一个实施例中，第二级的寄生电容是网络中最大的电容。 在另一个实施例中，无源网络耦合到级的输出，并且可以使用一个或多个电流注入电路来扩展电路的带宽。

公开(公告)号：US07522898B2

公开(公告)日：2009-04-21

申请号：US11142690

申请日：2005-06-01

Applicant: Mohammad E Heidari ,  Ahmad Mirzaei ,  Masoud Djafari ,  Mike Choi ,  Filipp A Baron ,  Alireza Mehrnia ,  Rahim Bagheri

Inventor： Mohammad E Heidari ,  Ahmad Mirzaei ,  Masoud Djafari ,  Mike Choi ,  Filipp A Baron ,  Alireza Mehrnia ,  Rahim Bagheri

IPC: H04B7/00

CPC classification number: H03L7/183 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0043 ,  H03L7/0891

Abstract: Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of divided signals and a frequency combination network including a plurality of mixers, the frequency combination network receiving one or more of the first plurality of divided signals and generating a plurality of synthesized signals having different frequencies. The frequency combination network may further include additional dividers and multiplexers for more flexibility in synthesizing different frequencies. In one embodiment, the frequency combination network is coupled to dividers in the feedback path of a phase locked loop. The present invention is particularly advantageous for synthesizing frequencies above one (1) gigahertz.

Abstract translation: 本发明的实施例包括频率合成器，其包括接收具有第一频率的第一信号和产生第一多个分频信号的第一多个分频器和包括多个混频器的频率组合网络，所述频率组合网络接收一个或多个 并产生具有不同频率的多个合成信号。 频率组合网络还可以包括附加的分频器和多路复用器，用于在合成不同频率时更灵活。 在一个实施例中，频率组合网络耦合到锁相环的反馈路径中的分频器。 本发明特别有利于合成高于一（1）吉赫兹的频率。

公开(公告)号：US20080122529A1

公开(公告)日：2008-05-29

申请号：US11501382

申请日：2006-08-09

Applicant: Rahim Bagheri ,  Ahmad Mirzaei

Inventor： Rahim Bagheri ,  Ahmad Mirzaei

IPC: H04B1/10

CPC classification number: H03H15/02

Abstract: Embodiments of the present invention include programmable filter circuits and methods. In one embodiment, the present invention includes a programmable filter for filtering an input signal comprising a storage element for storing a plurality of digital values representing a discrete time window function, and a plurality of filter channels, each channel comprising a multiplying digital-to-analog converter having a plurality of digital inputs coupled to the storage element and an analog input for receiving said input signal to be filtered, at least one capacitor having at least one terminal coupled to an output of the multiplying digital-to-analog converter, and a sampling device coupled between the at least one terminal of the at least one capacitor and an output of the filter. In another embodiment, the present invention includes a software defmed radio.

Abstract translation: 本发明的实施例包括可编程滤波器电路和方法。 在一个实施例中，本发明包括一个可编程滤波器，用于对输入信号进行滤波，该输入信号包括用于存储表示离散时间窗函数的多个数字值的存储元件和多个滤波器通道，每个通道包括乘法数字 - 模拟转换器，其具有耦合到存储元件的多个数字输入端和用于接收要滤波的所述输入信号的模拟输入端，至少一个电容器，其至少一个端子耦合到乘法数模转换器的输出端，以及 耦合在所述至少一个电容器的所述至少一个端子和所述滤波器的输出端之间的采样装置。 在另一个实施例中，本发明包括一个软件无线电装置。

公开(公告)号：US07633341B2

公开(公告)日：2009-12-15

申请号：US11584453

申请日：2006-10-20

Applicant: Mahdi Bagheri ,  Rahim Bagheri ,  Ahmad Mirzaei ,  Abbas Komijani ,  Edris Rostami ,  Masoud Djafari

Inventor： Mahdi Bagheri ,  Rahim Bagheri ,  Ahmad Mirzaei ,  Abbas Komijani ,  Edris Rostami ,  Masoud Djafari

IPC: H03F3/45

CPC classification number: H03F1/48 ,  H03F3/191 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/168 ,  H03F2200/36 ,  H03F2203/45302 ,  H03F2203/45318 ,  H03F2203/45342 ,  H03F2203/45354

Abstract: Embodiments of the present invention include circuits and methods with wide bandwidths. In one embodiment, parasitic capacitances of the output of a first stage and the input of a second stage are included in a network. The output of the first stage is coupled to the input of the network, and the input of the second stage is coupled to an intermediate node of the network. In one embodiment, the parasitic capacitance of the second stage is the largest capacitance in the network. In another embodiment, passive networks are coupled to the outputs of a stage, and one or more current injection circuits may be used to extend the bandwidth of the circuit.

Abstract translation: 本发明的实施例包括具有宽带宽的电路和方法。 在一个实施例中，第一级的输出和第二级的输入的寄生电容包括在网络中。 第一级的输出耦合到网络的输入，并且第二级的输入耦合到网络的中间节点。 在一个实施例中，第二级的寄生电容是网络中最大的电容。 在另一个实施例中，无源网络耦合到级的输出，并且可以使用一个或多个电流注入电路来扩展电路的带宽。

公开(公告)号：US20080317165A1

公开(公告)日：2008-12-25

申请号：US11820671

申请日：2007-06-19

Applicant: Mahdi Bagheri ,  Rahim Bagheri ,  Saeed Chehrazi ,  Masoud Djafari ,  Hassan Maarefi ,  Ahmad Mirzaei ,  Edris Rostami ,  Alireza Tarighat-Mehrabani

Inventor： Mahdi Bagheri ,  Rahim Bagheri ,  Saeed Chehrazi ,  Masoud Djafari ,  Hassan Maarefi ,  Ahmad Mirzaei ,  Edris Rostami ,  Alireza Tarighat-Mehrabani

IPC: H04L25/03

CPC classification number: H04B17/14 ,  H04B17/101

Abstract: In one embodiment the present invention includes a method of calibrating the frequency response of a transmitter comprising generating a plurality of calibration tones across a frequency range, coupling the plurality of calibration tones to an input of said transmitter, detecting the plurality of calibration tones at an output in said transmitter, and in accordance therewith, generating a plurality of calibration values, receiving digital data to be transmitted, the digital data comprising a plurality of frequency components in said frequency range, and calibrating said frequency components of said digital data using the calibration values.

Abstract translation: 在一个实施例中，本发明包括一种校准发射机的频率响应的方法，包括在频率范围内产生多个校准音调，将多个校准音调耦合到所述发射机的输入端，在多个校准音调 在所述发射机中输出，并且根据其产生多个校准值，接收要发射的数字数据，所述数字数据包括所述频率范围内的多个频率分量，并且使用校准来校准所述数字数据的所述频率分量 价值观。

公开(公告)号：US07403048B2

公开(公告)日：2008-07-22

申请号：US11142575

申请日：2005-06-01

Applicant: Mohammad E Heidari ,  Ahmad Mirzaei ,  Masoud Djafari ,  Rahim Bagheri

Inventor： Mohammad E Heidari ,  Ahmad Mirzaei ,  Masoud Djafari ,  Rahim Bagheri

IPC: H03B19/00

CPC classification number: H03K23/44

Abstract: Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I−) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q−) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.

Abstract translation: 本发明的实施例包括用于分割信号的电路和方法。 在一个实施例中，本发明包括分频器电路，其包括接收同相（I +）信号的至少一个第一分频器输入，接收同相（I-）信号的补码的至少一个第二分频器输入，至少一个 接收正交（Q +）信号的第三分频器输入端和接收正交（Q-）信号的补码的至少一个第四分频器输入端。 在一个实施例中，通过提供大于第二偏置电流的第一偏置电流来改善分频器的锁定范围。

公开(公告)号：US20070024330A1

公开(公告)日：2007-02-01

申请号：US11142705

申请日：2005-06-01

Applicant: Ahmad Mirzaei ,  Mohammad Heidari ,  Masoud Djafari ,  Rahim Bagheri

Inventor： Ahmad Mirzaei ,  Mohammad Heidari ,  Masoud Djafari ,  Rahim Bagheri

IPC: H03K23/00

CPC classification number: H03K23/52 ,  H03K3/012 ,  H03K3/356 ,  H03K23/44

Abstract: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

公开(公告)号：US20070024329A1

公开(公告)日：2007-02-01

申请号：US11142575

申请日：2005-06-01

Applicant: Mohammad Heidari ,  Ahmad Mirzaei ,  Masoud Djafari ,  Rahim Bagheri

Inventor： Mohammad Heidari ,  Ahmad Mirzaei ,  Masoud Djafari ,  Rahim Bagheri

IPC: H03K23/00

CPC classification number: H03K23/44

Abstract: Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I−) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q−) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.

Abstract translation: 本发明的实施例包括用于分割信号的电路和方法。 在一个实施例中，本发明包括分频器电路，其包括接收同相（I +）信号的至少一个第一分频器输入，接收同相（I-）信号的补码的至少一个第二分频器输入，至少一个 接收正交（Q +）信号的第三分频器输入端和接收正交（Q-）信号的补码的至少一个第四分频器输入端。 在一个实施例中，通过提供大于第二偏置电流的第一偏置电流来改善分频器的锁定范围。