摘要:
A method of on-line routing of permanent virtual circuits is disclosed. The method uses an exponential cost function based on the network state and virtual circuit parameters to determine paths for the virtual circuits without scaling. The method may also advantageously use information available when multiple virtual circuits are requested to determine paths for the virtual circuits. Additionally, the method allows the routing selection to be refined so that the total cost of routing all the virtual circuits is reduced.
摘要:
A method of routing a requested virtual circuit in a network advantageously uses information about concurrent requests for other virtual circuits. Each virtual circuit request in a set of concurrent requests is specified by one or more parameters and each virtual circuit request is routed as a function of one or more parameters of a plurality of the requests. Thereafter, the routing of each request in the set of requests is refined according to a cost function so that the total cost of routing is reduced.
摘要:
A system that incorporates teachings of the present disclosure may include, for example, a controller to determine a behavioral profile of an end user from packet traffic generated by activities of the end user, and share the behavioral profile with a network element for distributing targeted advertisements to the end user according to the behavioral profile. Additional embodiments are disclosed.
摘要:
A frame layer communications system for packet-switched virtual circuits that provides error detection when the link layer both corrupts and discards cells. An illustrative embodiment of the invention provides two error detection mechanisms: the first for the user-data and the second for certain control information. When the frame is segmented into cells, the control information and information relating to the second error detection mechanism are segmented into a single cell.
摘要:
In a local data distribution network configuration a plurality of bidirectional data distribution busses are each connected to a bus master control circuit at a terminal end of the bus. Connected to each of the data distribution busses are a plurality of passive outlets to which intelligent connectors or stations may be connected. Each station has a unique address and is utilized for individually coupling data processing devices to the bus. Grouped pluralities of the bus master control circuits are included within a bus termination hub facility. Data from any of the bus master control circuits may be transferred by the bus termination hub via a data trunk as part of a star type configuration, to a central switching circuit such as a virtual circuit switch. Direction of data flow on each of the bidirectional busses and periodic temporary synchronization of the stations is controlled in response to signals transmitted to the bus by the bus master control circuitry associated with that bus. A bus termination hub switching facility cooperates with the included group of bus master control circuits to interconnect data processing stations on the various busses with the virtual circuit switch via the trunk line and with each other.The bus termination hub facility further includes bus monitoring, status polling and maintenance facilities. A faulty bus will be disconnected if a fault is discovered during monitoring intervals. It will remain disconnected until the fault is corrected.
摘要:
A method and apparatus for generating at least one aggregate (e.g., a set of aggregates) for a given area of a network such that the number of aggregates is minimized subject to a maximum acceptable path selection error are disclosed. One operational benefit of the present method is that network administrators can select aggregates for an area based solely on the topology of the area without worrying about remaining areas of the OSPF network. Another benefit is that the present method enables trade-offs between the number of aggregates and the bound on the path selection error.
摘要:
A local area data distribution system includes a plurality of data processing stations connected to a common bus. Individual data processing stations contend with each other for access to the bus while the bus is held at a predetermined and controlled but overridable logic state by applying their priority code bit by bit to the bus and comparing the logic state of the bus with the bit they are applying thereto. A biasing arrangement holds the bus at the predetermined and controlled logic state during the contention interval at a signal level that may be easily overridden by an output of any one of the individual data processing stations.