公开(公告)号：US5404139A

公开(公告)日：1995-04-04

申请号：US924925

申请日：1992-08-05

申请人： Rajan Bhandari ,  Jonathan M. Soloff ,  Jonathan J. Stone

发明人： Rajan Bhandari ,  Jonathan M. Soloff ,  Jonathan J. Stone

IPC分类号： H03M7/40 ,  G06T9/00 ,  H03M7/42 ,  H04N1/41 ,  H03M13/22

CPC分类号： H03M7/425

摘要： A serial data decoder is described for decoding interleaved variable length and fixed length codes. The decoder includes a state machine which moves between a branching hierarchy of states in dependence upon the bits of received serial data. When the state machine reaches a state corresponding to a complete variable length code having been received, it then enters a delay state lasting for the length of time necessary to receive the following fixed length code prior to return to a reset state. The state machine can be implemented using a static ram 10 storing data including pointers for controlling the movements between states.

摘要翻译： 描述串行数据解码器用于解码交织的可变长度和固定长度码。 解码器包括根据所接收的串行数据的比特在状态的分支层次之间移动的状态机。 当状态机达到对应于已经接收到的完整可变长度代码的状态时，它然后在返回到复位状态之前进入持续所需时间长度的延迟状态，以接收以下固定长度代码。 状态机可以使用存储包括用于控制状态之间的移动的指针的数据的静态压头10来实现。

公开(公告)号：US5506687A

公开(公告)日：1996-04-09

申请号：US286386

申请日：1994-08-04

申请人： Clive H. Gillard ,  James H. Wilkinson ,  Michael J. Ludgate ,  Jonathan M. Soloff ,  Rajan Bhandari ,  Terence R. Hurley

发明人： Clive H. Gillard ,  James H. Wilkinson ,  Michael J. Ludgate ,  Jonathan M. Soloff ,  Rajan Bhandari ,  Terence R. Hurley

IPC分类号： G11B20/12 ,  B82B1/00 ,  H04N5/7826 ,  H04N5/92 ,  H04N5/926 ,  H04N7/24 ,  H04N9/797 ,  H04N9/80 ,  H04N9/804 ,  H04N9/808 ,  H04N9/88 ,  H04N9/888 ,  H04N9/79 ,  G11B5/02

CPC分类号： H04N5/926 ,  H04N5/78266 ,  H04N9/7973 ,  H04N9/8042 ,  H04N9/888 ,  H04N2009/8084

摘要： A digital video tape recording/playback system having a plurality of recording heads (A, B, C, D) on a rotating head mechanism 94 for recording slanting tracks 108 which extend diagonally across a tape 82 provides processing of video signals in a plurality of data processing channels with selective connection of the data processing channels to the recording heads such that data from a plurality of data processing channels are stored in respective portions of a slanting track (A+/A-; B+/B-; C+/C-; D+/D-). The data in each data processing channel and recorded in each track portion is sampled with a substantially even distribution over a field of video signals to provide for effective concealment of recording/playback errors. Preferably, two data processing channels are recorded on each track, the respective portions being located in upper and lower portions of the tape, respectively.

摘要翻译： 一种在旋转磁头机构94上具有多个记录头（A，B，C，D）的数字录像带记录/重放系统，用于记录沿着磁带82斜对角延伸的倾斜磁道108， 数据处理通道，数据处理通道选择性地连接到记录头，使得来自多个数据处理通道的数据被存储在倾斜磁道的相应部分（A + / A-; B + / B-; C + / C-; D + / D-）。 每个数据处理通道中记录在每个磁道部分中的数据在视频信号的场上以基本均匀的分布进行采样，以提供有效的隐藏记录/重放错误。 优选地，在每个轨道上记录两个数据处理通道，各个部分分别位于磁带的上部和下部。

公开(公告)号：US07627293B2

公开(公告)日：2009-12-01

申请号：US11617113

申请日：2006-12-28

申请人： Rajan Bhandari ,  Stephen Summerfield ,  Alan Barry Christie

发明人： Rajan Bhandari ,  Stephen Summerfield ,  Alan Barry Christie

IPC分类号： H04B1/04 ,  H04L25/03 ,  H03F1/26

CPC分类号： H03F1/3247

摘要： A corrective predistortion function is applied to a signal to compensate for or cancel out distortion that is introduced by a component that processes the signal. A disclosed example includes applying a corrective predistortion function to a transmitted signal used for wireless communications. A technique for selecting the corrective predistortion function includes determining a current power level of the signal. When the current power level is at or below a lift level between a maximum signal power level and a minimum signal power level, a corrective predistortion function corresponding to the lift level is applied to the signal. When the actual signal power level is above the lift level, a corrective predistortion function corresponding to the actual current power level is applied.

摘要翻译： 校正预失真函数被应用于信号以补偿或消除由处理信号的组件引入的失真。 公开的示例包括对用于无线通信的发送信号应用校正预失真函数。 用于选择校正预失真功能的技术包括确定信号的当前功率电平。 当当前功率电平处于或低于最大信号功率电平和最小信号功率电平之间的电平水平时，对应于电梯电平的校正预失真功能被施加到信号。 当实际信号功率电平高于电梯电平时，应用与实际当前功率电平对应的校正预失真功能。

公开(公告)号：US07483448B2

公开(公告)日：2009-01-27

申请号：US10797915

申请日：2004-03-10

申请人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

发明人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

IPC分类号： H04J3/06

CPC分类号： H04J3/0682

摘要： A method and system for network terminal clock synchronization includes determining a respective round trip delay time from a master terminal to each slave terminal and offsetting the clock of each slave terminal by an amount proportional to the respective determined round trip delay time such that the master terminal and each of the slave terminals have substantially the same point of reference in time. The method and system further include, in response to a trigger signal, determining a respective offset between the master clock of the master terminal and the clocks of each of the slave terminals and offsetting the clocks of each of the slave terminals by an amount proportional to the determined respective offset to synchronize the clocks of each of the slave terminals to the master clock of the master terminal.

摘要翻译： 一种用于网络终端时钟同步的方法和系统包括确定从主终端到每个从终端的相应往返行程延迟时间，并且将每个从终端的时钟偏移与各个确定的往返延迟时间成比例的量，使得主终端 并且每个从属终端在时间上基本上具有相同的参考点。 所述方法和系统还包括响应于触发信号，确定主终端的主时钟与每个从终端的时钟之间的相应偏移，并且将每个从终端的时钟偏移量与 所确定的各个偏移量使每个从终端的时钟同步到主终端的主时钟。

公开(公告)号：US20050201421A1

公开(公告)日：2005-09-15

申请号：US10797915

申请日：2004-03-10

申请人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

发明人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

IPC分类号： H04L12/56 ,  H04J3/06 ,  H04L7/00 ,  H04L12/28 ,  H04L12/64

CPC分类号： H04J3/0682

摘要： A method and system for network terminal clock synchronization includes determining a respective round trip delay time from a master terminal to each slave terminal and offsetting the clock of each slave terminal by an amount proportional to the respective determined round trip delay time such that the master terminal and each of the slave terminals have substantially the same point of reference in time. The method and system further include, in response to a trigger signal, determining a respective offset between the master clock of the master terminal and the clocks of each of the slave terminals and offsetting the clocks of each of the slave terminals by an amount proportional to the determined respective offset to synchronize the clocks of each of the slave terminals to the master clock of the master terminal.

摘要翻译： 一种用于网络终端时钟同步的方法和系统包括确定从主终端到每个从终端的相应往返行程延迟时间，并且将每个从终端的时钟偏移与各个确定的往返延迟时间成比例的量，使得主终端 并且每个从属终端在时间上基本上具有相同的参考点。 所述方法和系统还包括响应于触发信号，确定主终端的主时钟与每个从终端的时钟之间的相应偏移，并且将每个从终端的时钟偏移量与 所确定的各个偏移量使每个从终端的时钟同步到主终端的主时钟。

公开(公告)号：US5264847A

公开(公告)日：1993-11-23

申请号：US925179

申请日：1992-08-06

申请人： Rajan Bhandari

发明人： Rajan Bhandari

IPC分类号： G06T9/00 ,  H03M7/44 ,  H03M7/46 ,  H04N1/41 ,  H04N7/26 ,  H04N7/30

CPC分类号： H04N19/00 ,  H03M7/46 ,  H04N19/60 ,  H04N19/93 ,  H04N19/13 ,  H04N19/91

摘要： A data decoder is described for decoding interleaved first type code words [RUNLENGTH, SIZE] and second type code words [AMPLITUDE], each first type code word serving to define a runlength of constant values preceding a variable value defined by a following second type code word. The first type code words and the second type code words are fed to respective first and second pipeline delay units 22 and 24. The output from the first pipeline delay unit 22 is fed to a state machine 26 which reads the RUNLENGTH value and generates an INSERT ZEROS signal for a period proportional to the RUNLENGTH value followed by a signal triggering reading of the second pipeline delay unit 24. The INSERT ZEROS signal and the output of the second pipeline delay unit 24 are fed to a multiplexer 28 which selects between them to generate the appropriate OUTPUT signal. A swing buffer 10 is disposed upstream of the first and second pipeline delay units 22 and 24. The second pipeline delay unit 24 is also used to effect fixed length code decoding.

摘要翻译： 描述了用于解码交织的第一类型码字[RUNLENGTH，SIZE]和第二类型码字[AMPLITUDE]的数据解码器，每个第一类型码字用于定义由随后的第二类型码定义的变量值之前的常数值的游程长度 字。 第一类型码字和第二类型码字被馈送到相应的第一和第二流水线延迟单元22和24.来自第一流水线延迟单元22的输出被馈送到状态机26，其读取RUNLENGTH值并产生INSERT ZEROS信号与RUNLENGTH值成比例，随后是第二流水线延迟单元24的信号触发读取。INSERT ZEROS信号和第二流水线延迟单元24的输出被馈送到多路复用器28，多路复用器28在它们之间选择以产生 相应的OUTPUT信号。 摆动缓冲器10设置在第一和第二流水线延迟单元22和24的上游。第二流水线延迟单元24还用于实现固定长度码解码。

公开(公告)号：US20090073986A1

公开(公告)日：2009-03-19

申请号：US12277956

申请日：2008-11-25

申请人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

发明人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

IPC分类号： H04L12/56

CPC分类号： H04J3/0644 ,  H04L7/0008 ,  H04L67/325

摘要： A method and apparatus for guaranteeing packet delivery times in an asynchronous network includes generating a global timing schedule to synchronize the communication between the terminals of a network and, in response to at least one trigger, transmitting and receiving data according to the generated global timing schedule. To optimize bandwidth utilization, more than one terminal may transmit data during a specific time slot of each time frame of the global timing schedule as long as no more than one terminal attempts to transmit data to a common other terminal.

摘要翻译： 用于保证异步网络中的分组递送时间的方法和装置包括：生成全局定时调度，以使网络终端之间的通信同步，并且响应于至少一个触发，根据生成的全局时序调度发送和接收数据 。 为了优化带宽利用率，只要不超过一个终端尝试将数据发送到公共的其他终端，则多于一个终端可以在全局定时调度的每个时间帧的特定时隙内传送数据。

公开(公告)号：US20050201383A1

公开(公告)日：2005-09-15

申请号：US10797916

申请日：2004-03-10

申请人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

发明人： Rajan Bhandari ,  Miguel Dajer ,  Mahendra Tailor

IPC分类号： H04J3/06 ,  H04J3/16 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/54

CPC分类号： H04L49/90

摘要： A method, apparatus and system for the synchronized combining of packet data in a network includes sorting data packets received during a predetermined time period into groups according to for which communications device of the network the received data packets are intended. The data packets in each of the groups intended for the respective communications devices are respectively time aligned and orthogonally combined. The respectively combined data packets intended for each of the specific communications devices are subsequently transmitted to the intended device using a single header and in a substantially compressed format.

摘要翻译： 用于网络中的分组数据的同步组合的方法，装置和系统包括将在预定时间段期间接收到的数据分组分组为根据接收的数据分组所针对的网络的哪个通信设备。 针对各个通信设备的每个组中的数据分组分别是时间对准和正交组合。 用于每个特定通信设备的分别组合的数据分组随后使用单个报头并以基本压缩的格式发送到预期设备。

公开(公告)号：US5596674A

公开(公告)日：1997-01-21

申请号：US67117

申请日：1993-05-26

申请人： Rajan Bhandari ,  Clive H. Gillard

发明人： Rajan Bhandari ,  Clive H. Gillard

IPC分类号： G06T9/00 ,  H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  G10L3/02 ,  G10L9/00

CPC分类号： H03M7/425 ,  H04N19/60 ,  H04N19/13 ,  H04N19/39 ,  H04N19/91

摘要： A serial data coding system is described in which a state machine (FIG. 5) is provided having a plurality of branching hierarchies N, N+1 of states each corresponding to a different decoding table. Depending upon each received bit of serial data, the state machine moves through these branching hierarchies of states until states 88 corresponding to valid codes are reached whereupon a valid code is decoded and the state machine reset to the start of that branching hierarchy. If it is desired to move between branching hierarchies, then an internal table selecting word is inserted into the stream of serial data to move the state machine into a table incrementing state 90 where a jump to another branching hierarchy of states may be made. In order to cope with an externally applied switching signal Y/C for switching the state machine between branching hierarchies, the state machine is first moved into one of a plurality of transfer states A, C, D etc. These states are chosen to be distinct from all other states of the state machine within any branching hierarchies so there is no ambiguity as to which state should be adopted after receipt of the externally applied switching signal Y/C.

摘要翻译： 描述了串行数据编码系统，其中提供具有多个分支层次N，N + 1的状态机（图5），每个分支层次N，N + 1各自对应于不同的解码表。 根据每个接收到的串行数据位，状态机通过这些状态分支层次进行移动，直到达到对应于有效代码的状态88，然后对有效代码进行解码，并且状态机复位到该分支层次结构的开头。 如果希望在分支层次之间移动，则将内部表选择字插入到串行数据流中，以将状态机移动到表增加状态90，其中可以进行到另一分支状态分支层次的跳转。 为了处理在分支层次之间切换状态机的外部施加的切换信号Y / C，首先将状态机移动到多个传送状态A，C，D等中的一个。这些状态被选择为不同 从任何分支层级中的状态机的所有其他状态，所以在接收到外部施加的切换信号Y / C之后，应该采用何种状态的歧义。

公开(公告)号：US5543861A

公开(公告)日：1996-08-06

申请号：US401280

申请日：1995-03-09

申请人： Vincent C. Harradine ,  Howard J. Teece ,  Michael J. Ludgate ,  Rajan Bhandari ,  Gavin A. Walker

发明人： Vincent C. Harradine ,  Howard J. Teece ,  Michael J. Ludgate ,  Rajan Bhandari ,  Gavin A. Walker

IPC分类号： H04N5/91 ,  G11B20/10 ,  H04N5/92 ,  H04N5/926 ,  H04N5/937 ,  H04N9/64

CPC分类号： H04N5/937 ,  G11B2020/10953 ,  H04N5/9205 ,  H04N5/9261

摘要： A storage mechanism utilizing a single data recorder from which multiple channels of compressed video data may be simultaneously accessed. The data access to and from the data recorder via a single data access path takes place at a higher data rate (f.sub.1, f.sub.2) than the data rate (f.sub.3, f.sub.4) at which that compressed data needs to be decoded to support a video signal. A video router is used to direct the reproduced data stored within two data channel buffers to respective JPEG decoders where they are decompressed into a signal suitable for driving two digital monitors. In operation, a segment of compressed video data for one channel is recovered from the data recorder and stored within one of the buffers from which it is continuously read at a lower data rate (f.sub.3, f.sub.4). The data recorder then cues to another part of the medium from which data for the second channel is reproduced and stored within another buffer. The process is then repeated.

摘要翻译： 利用单个数据记录器的存储机构可以同时访问多个压缩视频数据的通道。 通过单个数据访问路径对数据记录器进行数据访问的数据速率（f1，f2）比要压缩数据需要解码以支持视频信号的数据速率（f3，f4）要高 。 视频路由器用于将存储在两个数据信道缓冲器内的再现数据引导到相应的JPEG解码器，在那里它们被解压缩成适合于驱动两个数字监视器的信号。 在操作中，从数据记录器恢复一个通道的压缩视频数据段，并存储在以较低数据速率（f3，f4）连续读取的一个缓冲器中。 数据记录器然后提示到媒体的另一部分，从该数据记录再生数据并存储在另一个缓冲器中。 然后重复该过程。