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1.发明申请Distributing Integrated Circuit Net Power Accurately in Power and Thermal Analysis 失效在功率和热分析中精确分配集成电路净功率公开(公告)号：US20090132834A1
公开(公告)日：2009-05-21
申请号：US11942030
申请日：2007-11-19
IPC分类号： G06F1/26
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/78 , G06F2217/80
摘要： A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.
摘要翻译： 提供了一种准确分配净功率的方法，系统和计算机程序产品。 在集成电路上模拟工作负载。 为集成电路中的一组网络和一组子网确定净交换活动。 基于净交换活动生成净交换数据。 使用净交换数据和每个单独网络或子网的净电容，为每个单独的网络和每个单独的子网计算净功率值。 每个计算的净功率值被分配给驱动单个网络或子网的一组源设备中的一个，其中净功率被精确地分配。 基于将每个净功率值分配给驱动单个网络或子网的一组源设备中的一个，生成净功率分配列表。
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2.发明授权Distributing integrated circuit net power accurately in power and thermal analysis 失效在电源和热分析中精确分配集成电路网络功率公开(公告)号：US07941680B2
公开(公告)日：2011-05-10
申请号：US11942030
申请日：2007-11-19
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/78 , G06F2217/80
摘要： A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.
摘要翻译： 提供了一种准确分配净功率的方法，系统和计算机程序产品。 在集成电路上模拟工作负载。 为集成电路中的一组网络和一组子网确定净交换活动。 基于净交换活动生成净交换数据。 使用净交换数据和每个单独网络或子网的净电容，为每个单独的网络和每个单独的子网计算净功率值。 每个计算的净功率值被分配给驱动单个网络或子网的一组源设备之一，其中净功率被精确地分配。 基于将每个净功率值分配给驱动单个网络或子网的一组源设备中的一个，生成净功率分配列表。
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3.发明申请公开(公告)号：US20110072406A1
公开(公告)日：2011-03-24
申请号：US12957881
申请日：2010-12-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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4.发明申请公开(公告)号：US20080125985A1
公开(公告)日：2008-05-29
申请号：US11530100
申请日：2006-09-08
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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5.发明授权公开(公告)号：US07720667B2
公开(公告)日：2010-05-18
申请号：US11530100
申请日：2006-09-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 第一硬件是用于响应于描述集成电路的宏执行第一软件，以及响应于第一软件的执行而产生一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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6.发明授权公开(公告)号：US08370780B2
公开(公告)日：2013-02-05
申请号：US12957881
申请日：2010-12-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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公开(公告)号：US07913201B2
公开(公告)日：2011-03-22
申请号：US12130644
申请日：2008-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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8.发明授权Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities 失效通过检测时钟门控机会来优化大规模集成（VLSI）设计中的功率的方法公开(公告)号：US07509606B2
公开(公告)日：2009-03-24
申请号：US11380126
申请日：2006-04-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A computer implemented power optimization method that generates statistics relating to the clock gating of a set of components in a VLSI design. A set of components, including those components which are not clock gated, are identified. The generation of statistics related to clock gating testing identify whether one or more components of the set of components may be clock gated.
摘要翻译： 一种计算机实现的功率优化方法，其生成与VLSI设计中的一组组件的时钟门控相关的统计信息。 识别一组组件，包括不是时钟门控的组件。 与时钟门控测试相关的统计信息的生成识别组件组中的一个或多个组件是否可以是时钟门控。
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公开(公告)号：US20080288910A1
公开(公告)日：2008-11-20
申请号：US12130644
申请日：2008-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes first hardware for executing first software in response to macros that describe the integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括用于响应于描述集成电路的宏执行第一软件的第一硬件，以及响应于第一软件的执行而生成一组常数。 第二硬件用于从第一硬件接收一组常数，以及响应于宏和一组常数执行第二软件，并且用于响应于第二软件的执行来估计集成电路的功耗。
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10.发明申请公开(公告)号：US20060190856A1
公开(公告)日：2006-08-24
申请号：US11044597
申请日：2005-01-27
申请人： Rajat Chaudhry , James Neely , Daniel Stasiak
发明人： Rajat Chaudhry , James Neely , Daniel Stasiak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power tables are created based upon the macro's input switching factor percentage and the clock activation percentage. These power tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate energy tables are produced.
摘要翻译： 提供了一种方法，计算机程序和装置，用于使用时钟门控输入来产生用于宏的电路能量模型。 电路能量模型用于估计系统功耗。 本发明使得能够为包含时钟门控输入的宏创建电路能量模型。 功率表基于宏的输入开关因子百分比和时钟激活百分比创建。 这些功率表是从最小数量的功率模拟产生的。 通过使用时钟激活百分比作为参数，产生精确的能量表。
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