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    Instruction unit having a partitioned cache
    1.
    发明授权
    Instruction unit having a partitioned cache 失效
    具有分区缓存的指令单元

    公开(公告)号：US5933850A

    公开(公告)日：1999-08-03

    申请号：US843795

    申请日：1997-04-21

    申请人： Rajendra Kumar ,  Rajiv Gupta ,  William S. Worley, Jr.

    发明人： Rajendra Kumar ,  Rajiv Gupta ,  William S. Worley, Jr.

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F9/3808 ,  G06F12/0875 ,  G06F9/30149 ,  G06F9/30178 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3863

    摘要： An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.

    摘要翻译： 公开了一种从用于序列控制的存储单元分离用于指令数据的存储单元的指令高速缓存。 指令在被存储到服务于主缓存的指令高速缓存之前被解码，而先前的层次级别的存储器以编码形式存储指令。 由于指令具有可变长度，所以指令高速缓存包括下一个地址确定电路以确定下一个指令地址。 本发明是有利的，因为存储单元的分离使得能够在当前指令的获取阶段期间产生下一个指令地址，从而避免了对另外必需的附加解码级的需要。 还公开了对于高速缓存未命中之后的任何高速缓存有用的旁路机制。

    Multi transform OFDM systems and methods with low peak to average power ratio signals
    3.
    发明授权
    Multi transform OFDM systems and methods with low peak to average power ratio signals 有权
    具有低峰值与平均功率比信号的多变换OFDM系统和方法

    公开(公告)号：US08995542B2

    公开(公告)日：2015-03-31

    申请号：US13913761

    申请日：2013-06-10

    申请人： Rajendra Kumar

    发明人： Rajendra Kumar

    IPC分类号： H04K1/10 ,  H04L27/28 ,  H04L27/26

    CPC分类号： H04L27/2602 ,  H04L27/2614 ,  H04L27/2615 ,  H04L27/2618

    摘要： Various embodiments of the invention are directed to methods and systems for multi transform OFDM transmitter and receivers with low peak to average power ratio (PAPR) signals, that have high bandwidth efficiency and are computational efficient. For example, various embodiments of the transmitter may utilize an architecture comprised of a baseband modulator, a serial to parallel converter, a bank of multiplicity NT orthonormal transforms unit, a bank of multiplicity NT inverse Fourier transforms unit, a dummy symbols generator, and a minimum PAPR evaluation unit for finding the optimum transform index n0. Various embodiments of the receiver may comprise of a transform index detection unit for the detection of the transform index imbedded in the OFDM signal.

    摘要翻译： 本发明的各种实施例涉及具有低峰值与平均功率比（PAPR）信号的具有高带宽效率并且具有计算效率的多变换OFDM发射机和接收机的方法和系统。 例如，发射机的各种实施例可以利用包括基带调制器，串行到并行转换器，多重组NT正交变换单元组，多重组NT逆傅里叶变换单元组，虚拟符号发生器和 用于找到最佳变换索引n0的最小PAPR评估单元。 接收机的各种实施例可以包括用于检测嵌入在OFDM信号中的变换索引的变换索引检测单元。

    Architectures and methods for code combiners
    4.
    发明授权
    Architectures and methods for code combiners 有权
    代码组合器的架构和方法

    公开(公告)号：US08982924B2

    公开(公告)日：2015-03-17

    申请号：US12660615

    申请日：2010-03-02

    申请人： Rajendra Kumar

    发明人： Rajendra Kumar

    IPC分类号： H04B1/00 ,  G06F7/00 ,  H04L27/00 ,  H04L27/20

    CPC分类号： G06F7/00 ,  H04L27/00 ,  H04L27/20

    摘要： Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of −1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.

    摘要翻译： 各种实施例涉及用于组合多个代码的系统和方法。 多个代码可以是具有可能的逻辑值为-1和+1的二进制代码，并且可以包括偶数个代码。 组合v0，k的输出可以由下式给出：v0 = sgn（vi），其中vi是第一时间的第一个多个代码的和。 呈现了各种代码中分配不同功率电平的实施例。

    Systems and methods for adaptive blind mode equalization
    5.
    发明授权
    Systems and methods for adaptive blind mode equalization 有权
    自适应盲模均衡的系统和方法

    公开(公告)号：US08711919B2

    公开(公告)日：2014-04-29

    申请号：US13434498

    申请日：2012-03-29

    申请人： Rajendra Kumar

    发明人： Rajendra Kumar

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0307 ,  H04L25/03292 ,  H04L27/3416 ,  H04L27/3845

    摘要： Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.

    摘要翻译： 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。

    Generalized frequency modulation
    6.
    发明授权
    Generalized frequency modulation 有权
    广义频率调制

    公开(公告)号：US08638890B2

    公开(公告)日：2014-01-28

    申请号：US13465606

    申请日：2012-05-07

    申请人： Rajendra Kumar

    发明人： Rajendra Kumar

    IPC分类号： H03D1/04

    CPC分类号： H04L27/12 ,  H04L27/156

    摘要： A receiver may comprise a complex mixer for converting the modulated signal to a complex modulated signal comprising a first in-phase component and a first quadrature component. The receiver may further comprise a digital demodulator. The digital demodulator may comprise at least one processor circuit programmed for applying a phase differencer for generating an output function in terms of a phase difference of the complex modulated signal. Applying the phase differencer may comprise converting the first in-phase component to a function of a phase difference of the first in-phase component expressed in digital time, and converting the first quadrature component to a function of the phase difference of the first quadrature component expressed in digital time. The at least one processor circuit of the digital demodulator may also be programmed for applying a four quadrant inverse tangent to the output function to generate the information signal.

    摘要翻译： 接收机可以包括用于将调制信号转换成包括第一同相分量和第一正交分量的复调制信号的复合混频器。 接收机还可以包括数字解调器。 数字解调器可以包括至少一个处理器电路，其被编程用于施加相位差分器，用于根据复调制信号的相位差产生输出函数。 应用相位差分器可以包括将第一同相分量转换为以数字时间表示的第一同相分量的相位差的函数，并将第一正交分量转换为第一正交分量的相位差的函数 以数字时代表达。 数字解调器的至少一个处理器电路也可以被编程为向输出功能施加四象限反正切以产生信息信号。

    FIFO buffer
    7.
    发明授权
    FIFO buffer 有权
    FIFO缓冲区

    公开(公告)号：US08612651B2

    公开(公告)日：2013-12-17

    申请号：US12599062

    申请日：2008-05-14

    申请人： Johannes Boonstra ,  Sundaravaradan Rangarajan ,  Rajendra Kumar

    发明人： Johannes Boonstra ,  Sundaravaradan Rangarajan ,  Rajendra Kumar

    IPC分类号： G06F3/00 ,  G06G5/00

    CPC分类号： G06F5/12

    摘要： A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

    摘要翻译： FIFO存储器电路用于在具有不同时钟域的电路之间进行接口。 电路具有FIFO存储器（10），由第一时钟域的时钟定时并且控制写入数据的存储器位置的写指针电路（16）以及由第二时钟的时钟脉冲定时的读指针电路 并控制读取数据的存储器位置。 读写指针电路采用灰度编码。 存储电路还包括一个重写写指针电路（30），它具有与写指针电路（16）同步增加的写指针地址，并且具有选择的开始写地址，使得重写写指针地址落在写指针之后 地址电路由与FIFO存储器（10）的大小对应的多个地址位置。 比较器（34）将读取指针电路地址与用于确定FIFO存储器的完整状态的重复写指针电路地址进行比较。

    SYSTEMS AND METHODS FOR ADAPTIVE BLIND MODE EQUALIZATION
    8.
    发明申请
    SYSTEMS AND METHODS FOR ADAPTIVE BLIND MODE EQUALIZATION 有权
    用于自适应盲模均衡的系统和方法

    公开(公告)号：US20130259113A1

    公开(公告)日：2013-10-03

    申请号：US13434498

    申请日：2012-03-29

    申请人： Rajendra Kumar

    发明人： Rajendra Kumar

    IPC分类号： H04L27/01 ,  H04B1/16

    CPC分类号： H04L25/03885 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0307 ,  H04L25/03292 ,  H04L27/3416 ,  H04L27/3845

    摘要： Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.

    摘要翻译： 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。

    RECEIVER FOR DETECTING SIGNALS IN THE PRESENCE OF HIGH POWER INTERFERENCE
    10.
    发明申请
    RECEIVER FOR DETECTING SIGNALS IN THE PRESENCE OF HIGH POWER INTERFERENCE 有权
    用于在高功率干扰下检测信号的接收器

    公开(公告)号：US20110033014A1

    公开(公告)日：2011-02-10

    申请号：US12537516

    申请日：2009-08-07

    申请人： Rajendra Kumar

    发明人： Rajendra Kumar

    IPC分类号： H04B1/10

    CPC分类号： H04B1/109

    摘要： A RF receiver that comprises: (i) a complex mixer for converting a version of the RF signal to a complex baseband signal comprising an in-phase component and a quadrature component; (ii) one or more analog-to-digital converters (ADCs) connected to the complex mixer for digitizing the in-phase component and the quadrature component of the complex baseband signal; and (iii) a digital signal processor (DSP) connected the one or more ADCs. The DSP is programmed to mitigate interference in the complex baseband signal by a process that comprises the steps of: (i) performing at least one cross correlation operation involving L-length segments of the digitized in-phase and quadrature components of the complex baseband signal; and (ii) concatenating the cross-correlated L-length segments of the digitized in-phase and quadrature components of the complex baseband signal to produce digitized interference mitigated in-phase and quadrature components of the complex baseband signal.

    摘要翻译： 一种RF接收机，包括：（i）用于将RF信号的版本转换成包括同相分量和正交分量的复基带信号的复合混频器; （ii）连接到复合混频器的一个或多个模数转换器（ADC），用于数字化复基带信号的同相分量和正交分量; 和（iii）连接所述一个或多个ADC的数字信号处理器（DSP）。 DSP被编程为通过包括以下步骤的处理来减轻复基带信号中的干扰：（i）执行涉及复基带信号的数字化同相和正交分量的L长度段的至少一个互相关运算 ; 并且（ii）连接复基带信号的数字化同相和正交分量的相关L长度段以产生减弱的复基带信号的同相和正交分量的数字化干扰。