公开(公告)号：US20130086383A1

公开(公告)日：2013-04-04

申请号：US13252713

申请日：2011-10-04

申请人： Rajiv Augusto Santos Galvao de Andrade ,  Steven A. Bade ,  Jeb R. Linton ,  Dimitrios Pendarakis ,  George C. Wilson ,  Lee H. Wilson

发明人： Rajiv Augusto Santos Galvao de Andrade ,  Steven A. Bade ,  Jeb R. Linton ,  Dimitrios Pendarakis ,  George C. Wilson ,  Lee H. Wilson

IPC分类号： H04L9/08 ,  H04L9/32

CPC分类号： H04L9/0897 ,  G06F21/57

摘要： A host machine provisions a virtual machine from a catalog of stock virtual machines. The host machine instantiates the virtual machine. The host machine configures the virtual machine, based on customer inputs, to form a customer's configured virtual machine. The host machine creates an image from the customer's configured virtual machine. The host machine unwraps a sealed customer's symmetric key to form a customer's symmetric key. The host machine encrypts the customer's configured virtual machine with the customer's symmetric key to form an encrypted configured virtual machine. The host machine stores the encrypted configured virtual machine to non-volatile storage.

摘要翻译： 主机从虚拟机目录中提供虚拟机。 主机实例化虚拟机。 主机根据客户输入配置虚拟机，形成客户配置的虚拟机。 主机从客户配置的虚拟机创建映像。 主机打开密封客户的对称密钥，形成客户的对称密钥。 主机使用客户的对称密钥加密客户配置的虚拟机，形成加密配置的虚拟机。 主机将加密的配置虚拟机存储到非易失性存储。

公开(公告)号：US20080052576A1

公开(公告)日：2008-02-28

申请号：US11464393

申请日：2006-08-14

申请人： Mark A. Brandyberry ,  Lee H. Wilson

发明人： Mark A. Brandyberry ,  Lee H. Wilson

IPC分类号： G01R31/28

CPC分类号： G06F11/2242 ,  G01R31/318533

摘要： Methods, apparatus, and products for processor fault isolation are disclosed that include sending, by an embedded system microcontroller to a programmable logic device (‘PLD’) a selection signal identifying one processor for boundary scan operations; sending boundary scan input signals to be sent to the identified processor; multiplexing by the PLD the boundary scan input signals to the identified processor; and sending boundary scan output signals returned from the identified processor. Methods, apparatus, and products for processor fault isolation are also disclosed that include connecting two or more processors in a boundary scan test chain, the connecting carried out by a PLD of a computer, the PLD further connected to sense lines carrying presence signals indicating whether processors are present in the computer; and including in the chain all processors indicated present according to presence signals.

摘要翻译： 公开了用于处理器故障隔离的方法，装置和产品，其包括由嵌入式系统微控制器向可编程逻辑器件（“PLD”）发送识别用于边界扫描操作的一个处理器的选择信号; 发送要发送到所识别的处理器的边界扫描输入信号; 通过PLD将边界扫描输入信号复用到识别的处理器; 并发送从所识别的处理器返回的边界扫描输出信号。 还公开了用于处理器故障隔离的方法，装置和产品，其包括在边界扫描测试链中连接两个或多个处理器，由计算机的PLD执行的连接，PLD进一步连接到传送线，其携带存在信号，指示是否 处理器存在于计算机中; 并且在链中包括所有处理器根据存在信号指示存在。

公开(公告)号：US4939735A

公开(公告)日：1990-07-03

申请号：US222679

申请日：1988-07-21

申请人： Kenneth J. Fredericks ,  Joseph J. Kubik ,  Michael R. Wiegand ,  Lee H. Wilson

发明人： Kenneth J. Fredericks ,  Joseph J. Kubik ,  Michael R. Wiegand ,  Lee H. Wilson

IPC分类号： G06F11/08 ,  G06F13/12 ,  G06F13/42 ,  H04L1/00

CPC分类号： G06F13/122 ,  G06F13/4226 ,  G06F11/08

摘要： An information handling system includes a processor with one or more channels for communicating to peripheral devices controlled by peripheral device controllers, and one or more serial data links between the channels and the peripheral controllers. Data is transmitted over the serial data link between the channels and the controllers in a frame format, wherein each frame includes a number of eight-bit characters selected so that all standard parallel interface tag and data lines are transmitted in a single frame with a high degree of error immunity resulting from selection of idle characters and frame start characters having the mutual characteristic that single and double bit errors in the idle characters do not create an erroneous indication of a start character in the system.

公开(公告)号：US09053315B2

公开(公告)日：2015-06-09

申请号：US13536570

申请日：2012-06-28

申请人： Robert J. Donovan ,  Joseph C. Lindsay ,  Randall S. Nelson ,  Christopher A. Peterson ,  Darrel W. Raknerud ,  Taylor L. Schreck ,  Judith Trousdell ,  Lee H. Wilson ,  John C. Wingertsman, III ,  Andrew W. Wojtowicz ,  Tokunbo Adeshiyan

发明人： Robert J. Donovan ,  Joseph C. Lindsay ,  Randall S. Nelson ,  Christopher A. Peterson ,  Darrel W. Raknerud ,  Taylor L. Schreck ,  Judith Trousdell ,  Lee H. Wilson ,  John C. Wingertsman, III ,  Andrew W. Wojtowicz ,  Tokunbo Adeshiyan

IPC分类号： H01L29/00 ,  G06F21/42 ,  G06F21/57

CPC分类号： G06F21/42 ,  G06F21/57 ,  G06F2221/2107 ,  G06F2221/2129

摘要： A method, system, and computer-readable storage media for granting a device access to a managed group are disclosed. Identification information may be exchanged between a management device in the managed group and a managed device through a secure first channel. If the identification information is verified by the management device, the managed device may be granted access to the managed group through the secure first channel. If access is granted, the managed device may access the managed group through a secure communication session on a network. If the identification information is not verified, the management device may send a cryptographic key to the managed device through the secure first channel. The cryptographic key may be used to create an encrypted communication session between the managed device and management device over the network.

摘要翻译： 公开了一种用于授予对被管理组的设备访问的方法，系统和计算机可读存储介质。 识别信息可以通过安全第一信道在被管理组中的管理设备与被管理设备之间交换。 如果管理装置验证了识别信息，则可以通过安全第一信道向被管理设备授予对被管理组的访问。 如果授权访问，则受管设备可以通过网络上的安全通信会话访问受管理组。 如果识别信息未被验证，则管理设备可以通过安全第一信道向被管理设备发送加密密钥。 加密密钥可以用于通过网络在被管理设备和管理设备之间创建加密的通信会话。

公开(公告)号：US07853638B2

公开(公告)日：2010-12-14

申请号：US12141346

申请日：2008-06-18

申请人： Lee H. Wilson ,  Kirby L. Watson ,  Vinh B. Lu ,  Mark W. Mueller ,  Daniel E. Hurlimann

发明人： Lee H. Wilson ,  Kirby L. Watson ,  Vinh B. Lu ,  Mark W. Mueller ,  Daniel E. Hurlimann

IPC分类号： G06F15/16

CPC分类号： G06F13/4022

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for addressing deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and for flexibly configurable multi-CPU supported hypertransport switching is provided. The design structure can include a hypertransport switching data processing system. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

摘要翻译： 体现在机器可读存储介质中的用于设计，制造和/或测试用于针对多CPU系统的基于超传输的切换以及用于灵活可配置的多CPU支持的超传输切换的本领域的缺陷的设计的设计结构是 提供。 该设计结构可以包括超传输交换数据处理系统。 该系统可以包括一个CPU和至少两个I / O桥。 每个I / O桥可以提供从CPU驱动到相应的外围设备的数据的通信路径。 值得注意的是，该系统可以包括灵活配置的超传输交换机。 交换机可以包括将CPU适配到两个I / O桥的第一配置，以及将CPU适配到第一个I / O桥以及第二CPU到第二个I / O桥的第二配置 。

公开(公告)号：US20080256222A1

公开(公告)日：2008-10-16

申请号：US12141346

申请日：2008-06-18

申请人： Lee H. Wilson ,  Kirby L. Watson ,  Vinh B. Lu ,  Mark W. Mueller ,  Daniel E. Hurlimann

发明人： Lee H. Wilson ,  Kirby L. Watson ,  Vinh B. Lu ,  Mark W. Mueller ,  Daniel E. Hurlimann

IPC分类号： G06F15/177

CPC分类号： G06F13/4022

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for addressing deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and for flexibly configurable multi-CPU supported hypertransport switching is provided. The design structure can include a hypertransport switching data processing system. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

摘要翻译： 体现在机器可读存储介质中的用于设计，制造和/或测试用于针对多CPU系统的基于超传输的切换以及用于灵活可配置的多CPU支持的超传输切换的本领域的缺陷的设计的设计结构是 提供。 该设计结构可以包括超传输交换数据处理系统。 该系统可以包括一个CPU和至少两个I / O桥。 每个I / O桥可以提供从CPU驱动到相应的外围设备的数据的通信路径。 值得注意的是，该系统可以包括灵活配置的超传输交换机。 交换机可以包括将CPU适配到两个I / O桥的第一配置，以及将CPU适配到第一个I / O桥以及第二CPU到第二个I / O桥的第二配置 。

公开(公告)号：US20150051025A1

公开(公告)日：2015-02-19

申请号：US14530969

申请日：2014-11-03

申请人： Lee H. Wilson

发明人： Lee H. Wilson

IPC分类号： A63B71/06

CPC分类号： A63B67/002 ,  A63B2071/0625 ,  A63B2208/0252 ,  A63B2220/62 ,  A63B2243/0037

摘要： Roundball is a sports event that is based on the same primitive activity that forms the basis of three other games, namely, basketball, 21st Century Challenge America Basketball Game, and Method for Playing a Basketball-Type Game. The latter two are patented. All four are singular games by virtue of their completely different formats. Roundball games are composed of rounds, like boxing matches; and the winner of the game is the team that accumulates the majority of the points in each of the majority of the rounds. Roundball games will be suspenseful from start to finish, with clear and reasonable results. There is good reason to expect that professional Roundball will become a strong competitor for a share of the multi-billion-dollar entertainment industry market. There is no record of anyone else having conceived the same idea; which is strong empirical evidence that your petitioner is the inventor of Roundball.

摘要翻译： Roundball是一个基于同样的原始活动的体育赛事，形成了其他三场比赛的基础，即篮球，21世纪挑战赛美式篮球比赛和打篮球式比赛的方式。 后两者获得专利。 所有这四个都是单一的游戏，凭借完全不同的格式。 圆球比赛由圆形比赛组成，如拳击比赛; 而比赛的获胜者是在大多数回合中积累了大部分积分的球队。 圆球比赛从头到尾都是悬念，结果清晰合理。 有充分的理由期望专业的Roundball将成为数十亿美元娱乐产业市场份额的强大竞争对手。 没有任何其他人构思同样的想法的记录; 这是强有力的实证证据，你的请愿者是Roundball的发明者。

公开(公告)号：US07797475B2

公开(公告)日：2010-09-14

申请号：US11627514

申请日：2007-01-26

申请人： Lee H. Wilson ,  Kirby L. Watson ,  Vinh B. Lu ,  Mark W. Mueller ,  Daniel E. Hurlimann

发明人： Lee H. Wilson ,  Kirby L. Watson ,  Vinh B. Lu ,  Mark W. Mueller ,  Daniel E. Hurlimann

IPC分类号： G06F13/36

CPC分类号： G06F13/4022

摘要： Embodiments of the invention address deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and provide a method, system and computer program product for flexibly configurable multi-CPU supported hypertransport switching. In one embodiment of the invention, a hypertransport switching data processing system can be provided. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

摘要翻译： 本发明的实施例解决了关于多CPU系统的基于超传输的交换的本领域的缺点，并提供了用于灵活可配置的多CPU支持的超传输交换的方法，系统和计算机程序产品。 在本发明的一个实施例中，可以提供超传输切换数据处理系统。 该系统可以包括一个CPU和至少两个I / O桥。 每个I / O桥可以提供从CPU驱动到相应的外围设备的数据的通信路径。 值得注意的是，该系统可以包括灵活配置的超传输交换机。 交换机可以包括将CPU适配到两个I / O桥的第一配置，以及将CPU适配到第一个I / O桥以及第二CPU到第二个I / O桥的第二配置 。

公开(公告)号：US20100125731A1

公开(公告)日：2010-05-20

申请号：US12270888

申请日：2008-11-14

申请人： Shiva R. Dasari ,  Lee H. Wilson ,  Scott N. Durham ,  Sumeet Kochar ,  William B. Schwartz ,  Kenneth A. Goldman

发明人： Shiva R. Dasari ,  Lee H. Wilson ,  Scott N. Durham ,  Sumeet Kochar ,  William B. Schwartz ,  Kenneth A. Goldman

IPC分类号： H04L9/00

CPC分类号： G06F9/5061 ,  G06F21/57 ,  G06F2221/2105

摘要： Method, apparatus and computer program product are provided for operating a plurality of computer nodes while maintaining trust. A primary computer node and at least one secondary computer node are connected into a cluster, wherein each of the clustered computer nodes includes a trusted platform module (TPM) that is accessible to software and includes security status information about the respective computer node. Each clustered computer node is then merged into a single node with only the TPM of the primary computer node being accessible to software. The TPM of the primary computer node is updated to include the security status information of each TPM in the cluster. Preferably, the step of merging is controlled by power on self test (POST) basic input output system (BIOS) code associated with a boot processor in the primary node.

摘要翻译： 提供了用于操作多个计算机节点同时保持信任的方法，装置和计算机程序产品。 主计算机节点和至少一个辅助计算机节点连接到集群中，其中每个集群计算机节点包括可由软件访问的可信平台模块（TPM），并且包括关于相应计算机节点的安全状态信息。 然后将每个集群计算机节点合并到单个节点，只有主计算机节点的TPM才能被软件访问。 更新主计算机节点的TPM以包括集群中每个TPM的安全状态信息。 优选地，合并步骤由与主节点中的引导处理器相关联的上电自检（POST）基本输入输出系统（BIOS）代码来控制。

公开(公告)号：US07594144B2

公开(公告)日：2009-09-22

申请号：US11464364

申请日：2006-08-14

申请人： Mark A. Brandyberry ,  Shiva R. Dasari ,  Daniel E. Hurlimann ,  Bruce J. Wilkie ,  Lee H. Wilson ,  Christopher L. Wood

发明人： Mark A. Brandyberry ,  Shiva R. Dasari ,  Daniel E. Hurlimann ,  Bruce J. Wilkie ,  Lee H. Wilson ,  Christopher L. Wood

IPC分类号： G06F11/00

CPC分类号： G06F11/0787 ,  G06F11/0745

摘要： Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.

摘要翻译： 公开了用于处理计算机上的致命计算机硬件错误的方法和装置，包括在发生致命硬件错误时停止计算机的数据处理操作; 由芯片组的源芯片向可编程逻辑器件发出致命硬件错误的发生; 信号由可编程逻辑器件向嵌入式系统微控制器发生致命的硬件错误; 嵌入式系统微控制器通过芯片芯片寄存器中的至少一个边带总线读取有关致命硬件错误原因的信息; 并将嵌入式系统微控制器存储在嵌入式系统微控制器的非易失性随机存取存储器中。