公开(公告)号：US5793233A

公开(公告)日：1998-08-11

申请号：US655475

申请日：1996-05-30

申请人： Ramachandra P. Kunda ,  Gary Goldman

发明人： Ramachandra P. Kunda ,  Gary Goldman

IPC分类号： H03L7/085 ,  H03L7/00

CPC分类号： H03L7/085

摘要： A phase detection signal is generated with a phase detection logic pipeline and its associated tapped pipeline signal combinational logic circuit. The phase detection logic pipeline generates phase detection logic pipeline output signals from a first input clock signal and a second input clock signal. The first input clock signal is applied to a first flip-flop of a set of serially connected flip-flops to generate a pipeline signal. The pipeline signal is driven through the set of serially connected flip-flops by the second clock input signal. Logic pipeline output nodes connected between the serially connected flip-flops carry the phase detection logic pipeline output signals. The phase detection logic pipeline output signals are applied to the tapped pipeline signal combinational logic circuit, which logically combines the signals to generate the phase detection signal.

摘要翻译： 相位检测信号用相位检测逻辑流水线及其相关联的抽头流水线信号组合逻辑电路产生。 相位检测逻辑流水线从第一输入时钟信号和第二输入时钟信号产生相位检测逻辑流水线输出信号。 第一输入时钟信号被施加到一组串联的触发器的第一触发器以产生流水线信号。 流水线信号通过第二时钟输入信号通过串联的触发器组驱动。 连接在串联的触发器之间的逻辑管线输出节点携带相位检测逻辑管线输出信号。 相位检测逻辑流水线输出信号被施加到抽头流水线信号组合逻辑电路，其逻辑组合信号以产生相位检测信号。

公开(公告)号：US5675728A

公开(公告)日：1997-10-07

申请号：US679318

申请日：1996-07-12

申请人： Ramachandra P. Kunda ,  Saied Bozorgui-Nesbat ,  Hong Hao

发明人： Ramachandra P. Kunda ,  Saied Bozorgui-Nesbat ,  Hong Hao

IPC分类号： H01L21/82 ,  G01R31/3183 ,  G06F17/50 ,  G01R31/28

CPC分类号： G01R31/318357 ,  G01R31/318328 ,  G06F17/5031

摘要： A method for identifying false paths in a digital circuit. A list of paths corresponding to the digital circuit is either provided or generated. For each path, an AND gate is created. For each element in the path, the off-path signals of the monitor circuits corresponding to the elements of the path are coupled to the input of the AND gate. A plurality of different signals are input to the digital circuit in an attempt to generate a "1" at the output of the AND gate. A false timing path signal is generated for that path if the AND gate does not output a "1" within a pre-determined amount of time. This process is repeated for each path of the digital circuit to identify all false timing paths.

摘要翻译： 一种用于识别数字电路中的虚路径的方法。 提供或生成与数字电路相对应的路径的列表。 对于每个路径，创建一个与门。 对于路径中的每个元件，对应于路径的元件的监视器电路的离开路径信号被耦合到与门的输入端。 多个不同的信号被输入到数字电路，试图在与门的输出处产生“1”。 如果AND门在预定时间内没有输出“1”，则为该路径生成错误的定时路径信号。 对于数字电路的每个路径重复该过程以识别所有假定时路径。

公开(公告)号：US5528165A

公开(公告)日：1996-06-18

申请号：US458001

申请日：1995-06-01

申请人： Slobodan Simovich ,  Marc E. Levitt ,  Srinivas Nori ,  Ramachandra P. Kunda

发明人： Slobodan Simovich ,  Marc E. Levitt ,  Srinivas Nori ,  Ramachandra P. Kunda

IPC分类号： G06F11/00 ,  G06F11/08 ,  H03K19/21

CPC分类号： G06F11/0763 ,  G06F11/085

摘要： A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.

摘要翻译： 用于确定一组逻辑信号的逻辑状态的有效性的逻辑信号有效性验证器包括用于确定何时所有逻辑信号处于非活动信号状态的无效信号故障监视器和用于确定何时 多于一个逻辑信号处于活动信号状态。 在逻辑信号为差分的情况下，逻辑信号有效性验证器还包括差分信号故障监视器，用于确定何时对应的差分逻辑信号对处于相同的有效或无效信号状态。

公开(公告)号：US5570376A

公开(公告)日：1996-10-29

申请号：US318378

申请日：1994-10-05

申请人： Ramachandra P. Kunda ,  Adam C. Malamy ,  Marc Levitt

发明人： Ramachandra P. Kunda ,  Adam C. Malamy ,  Marc Levitt

IPC分类号： G06F11/25 ,  G06F11/22

CPC分类号： G06F11/2257

摘要： Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets. The lists of candidate faulty gates are input to an X-Y location tool which determines the physical location on the integrated circuit of each of the candidate faulty gates to facilitate the efficient examination of each of the candidate faulty gates by test personnel.

摘要翻译： 为了进行故障诊断，通过执行诸如JTAG测试等全扫描测试的故障列表输出的部分交错，生成集成电路内的候选故障列表。 故障列表表示可能负责在输出测试向量与全扫描测试提供的预期测试向量之间产生不匹配位的所有候选故障。 通过首先确定与每个不匹配位相关联的所有列表内的每个候选故障的出现次数来执行部分交集。 然后，仅选择发生至少预选次数的故障。 以这种方式，基于故障集之间的相对交点，产生候选故障门的列表。 候选故障门的列表被输入到X-Y定位工具，其确定每个候选故障门的集成电路上的物理位置，以便于测试人员有效地检查每个候选故障门。