公开(公告)号：US12189523B2

公开(公告)日：2025-01-07

申请号：US18210387

申请日：2023-06-15

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/10 ,  G11C7/22 ,  G11C8/10

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US11720485B2

公开(公告)日：2023-08-08

申请号：US17728791

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  H05K999/99 ,  G06F2212/2024 ,  G11C2207/107

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US20150178187A1

公开(公告)日：2015-06-25

申请号：US14637369

申请日：2015-03-03

Applicant: Rambus Inc.

Inventor： Thomas Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract translation: 存储器访问命令，列地址和多个写入数据值经由外部信令链路在集成电路存储器芯片内被接收。 响应于存储器访问命令，集成电路存储器芯片（i）解码列地址以从构成读出放大器组的多个读出放大器中选择地址指定的读出放大器，（ii）读取第一数据，构成 通过多个读取数据值，从地址指定的读出放大器中，和（iii）用地址指定的读出放大器中的第一数据用由一个或多个写数据值构成的第二数据和一个或多个 的读取数据值。

公开(公告)号：US20230325309A1

公开(公告)日：2023-10-12

申请号：US18210387

申请日：2023-06-15

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G11C7/22 ,  G11C8/10 ,  G11C7/1006 ,  G11C7/1039 ,  H05K999/99 ,  G11C2207/107 ,  G06F2212/2024

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US20220253378A1

公开(公告)日：2022-08-11

申请号：US17728791

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C7/10 ,  G11C8/10

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US11748252B2

公开(公告)日：2023-09-05

申请号：US17540437

申请日：2021-12-02

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  H05K999/99 ,  G06F2212/2024 ,  G11C2207/107

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US20220206936A1

公开(公告)日：2022-06-30

申请号：US17540437

申请日：2021-12-02

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US09898400B2

公开(公告)日：2018-02-20

申请号：US15497126

申请日：2017-04-25

Applicant: Rambus Inc.

Inventor： Thomas A. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G11C7/10 ,  G11C7/22 ,  G11C8/10

CPC classification number: G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US20170293552A1

公开(公告)日：2017-10-12

申请号：US15497126

申请日：2017-04-25

Applicant: Rambus Inc.

Inventor： Thomas A. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US11204863B2

公开(公告)日：2021-12-21

申请号：US16735303

申请日：2020-01-06

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.