公开(公告)号：US20190212948A1

公开(公告)日：2019-07-11

申请号：US16236946

申请日：2018-12-31

Applicant: Rambus Inc.

Inventor： Michael L. TAKEFMAN ,  Maher AMER ,  Riccardo Badalone

IPC: G06F3/06 ,  G06F9/4401 ,  G06F13/20 ,  G06F13/42 ,  H03M13/27 ,  H04L9/06 ,  G06F12/06 ,  G06F12/02 ,  G06F11/10 ,  H03M13/05 ,  G06F13/40

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F9/4406 ,  G06F11/1016 ,  G06F11/1076 ,  G06F12/0246 ,  G06F12/0607 ,  G06F13/20 ,  G06F13/404 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4282 ,  G06F2212/1008 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7208 ,  H03M13/05 ,  H03M13/27 ,  H04L9/0662

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.