公开(公告)号：US20230125262A1

公开(公告)日：2023-04-27

申请号：US17963065

申请日：2022-10-10

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Dongyun LEE ,  Thomas VOGELSANG ,  Steven C. WOO

IPC: G02B6/293 ,  G02B6/12 ,  H04B10/50

Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

公开(公告)号：US20250061935A1

公开(公告)日：2025-02-20

申请号：US18796915

申请日：2024-08-07

Applicant: Rambus Inc.

Inventor： Dongyun LEE ,  Mark D. KELLAM ,  Joohee KIM

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/419

Abstract: An interposer interconnecting a first integrated circuit and a second integrated circuit includes active circuitry. The “active” interposer converts high-speed signals into lower-speed, but more parallelized, signals for transmission across the active interposer. The parallelized signals may be buffered or amplified at intervals while crossing the active interposer. The high-speed to low-speed, and back, conversions may be performed by an appropriately configured and controlled multiplexer/demultiplexer circuitry The supply voltages for some interposer circuits may be different than the supply voltages for the interfaces with the first and second integrated circuit. One or more of the interconnected integrated circuits may supply, and/or calibrate the supply voltages for the interposer circuitry. Timing signals provided by one or more of the interconnected integrated circuits may also be calibrated using circuitry on the active interposer.

公开(公告)号：US20230410898A1

公开(公告)日：2023-12-21

申请号：US18031487

申请日：2021-10-05

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM

IPC: G11C11/42 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C11/42 ,  G11C16/12 ,  G11C16/102

Abstract: A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing. The wavelength of the light is selected such that the photons impinging on the flash memory cell have an energy that approaches the barrier height (conduction band offset) of the tunnel insulator. Illuminating the flash memory cell during programming/erase increases the tunneling current through the tunnel insulator by way of the photon assisted tunneling (PAT) effect.

公开(公告)号：US20230008889A1

公开(公告)日：2023-01-12

申请号：US17852169

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  Mark D. KELLAM

IPC: G11C11/42 ,  G02B6/12

Abstract: Multidrop optical connections are used for an optical memory module. Multiple buffer integrated circuits on a module each receive information from the host system using different wavelengths of light transmitted on the same waveguide. Multiple buffer integrated circuits each transmit information back to the CPU using different wavelengths of light transmitted on another waveguide. Wavelength resonant ring couplers disposed on the buffer integrated circuits are used to separate the wavelength being received by a particular buffer integrated circuit from the wavelengths of light destined for other buffer integrated circuits on the same waveguide. Wavelength resonant ring modulators also disposed on the buffer integrated circuits modulate specific wavelengths of light unique to each buffer integrated circuit to transmit information to the CPU.

公开(公告)号：US20220269436A1

公开(公告)日：2022-08-25

申请号：US17627478

申请日：2020-07-06

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Steven C. WOO ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC: G06F3/06

Abstract: An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.