公开(公告)号：US20250119148A1

公开(公告)日：2025-04-10

申请号：US18927163

申请日：2024-10-25

Applicant: Rambus Inc.

Inventor： Panduka WIJETUNGA ,  Catherine Chen

IPC: H03L7/081 ,  H03L7/097

Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

公开(公告)号：US20230188145A1

公开(公告)日：2023-06-15

申请号：US18070713

申请日：2022-11-29

Applicant: Rambus Inc.

Inventor： Panduka WIJETUNGA ,  Catherine CHEN

IPC: H03L7/081 ,  H03L7/097

CPC classification number: H03L7/0814 ,  H03L7/0816 ,  H03L7/097

Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.