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公开(公告)号：US11809345B2
公开(公告)日：2023-11-07
申请号：US17677714
申请日：2022-02-22
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
CPC classification number: G06F13/1689 , G06F13/1673 , G06F13/1678 , G06F13/4022 , G06F13/4265
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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2.发明申请公开(公告)号：US20210049119A1
公开(公告)日：2021-02-18
申请号：US17021024
申请日：2020-09-15
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US10146608B2
公开(公告)日：2018-12-04
申请号：US15090399
申请日：2016-04-04
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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4.发明授权公开(公告)号：US12210467B2
公开(公告)日：2025-01-28
申请号：US18480344
申请日：2023-10-03
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , John Eric Linstadt , Catherine Chen
Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US11953981B2
公开(公告)日：2024-04-09
申请号：US18092556
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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Patent Agency Ranking
公开(公告)号：US20250119148A1
公开(公告)日：2025-04-10
申请号：US18927163
申请日：2024-10-25
Applicant: Rambus Inc.
Inventor： Panduka WIJETUNGA , Catherine Chen
Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.
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公开(公告)号：US12211583B2
公开(公告)日：2025-01-28
申请号：US18021442
申请日：2021-08-24
Applicant: Rambus Inc.
Inventor： Torsten Partsch , Shahram Nikoukary , Catherine Chen
Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.
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公开(公告)号：US20230298642A1
公开(公告)日：2023-09-21
申请号：US18021442
申请日：2021-08-24
Applicant: Rambus Inc.
Inventor： Torsten Partsch , Shahram Nikoukary , Catherine Chen
CPC classification number: G11C7/1084 , G11C7/1057 , G11C7/222
Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.
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公开(公告)号：US11573849B2
公开(公告)日：2023-02-07
申请号：US17236445
申请日：2021-04-21
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US12298842B2
公开(公告)日：2025-05-13
申请号：US18586907
申请日：2024-02-26
Applicant: Rambus Inc.
Inventor： Thomas J. Giovannini , Catherine Chen , Scott C. Best , John Eric Linstadt , Frederick A. Ware
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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