公开(公告)号：US20180341603A1

公开(公告)日：2018-11-29

申请号：US15992112

申请日：2018-05-29

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/32 ,  G06F12/02

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US11200181B2

公开(公告)日：2021-12-14

申请号：US16828570

申请日：2020-03-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3234 ,  G06F12/02

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US12189548B2

公开(公告)日：2025-01-07

申请号：US17534180

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/3234 ,  G06F12/02 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US20170249265A1

公开(公告)日：2017-08-31

申请号：US15458166

申请日：2017-03-14

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

公开(公告)号：US09996485B2

公开(公告)日：2018-06-12

申请号：US15458166

申请日：2017-03-14

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

公开(公告)号：US20220147472A1

公开(公告)日：2022-05-12

申请号：US17534180

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US20200293469A1

公开(公告)日：2020-09-17

申请号：US16828570

申请日：2020-03-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/3234

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US09632956B2

公开(公告)日：2017-04-25

申请号：US14874324

申请日：2015-10-02

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/02

CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.