公开(公告)号：US20070050564A1

公开(公告)日：2007-03-01

申请号：US11215604

申请日：2005-08-30

申请人： Ramesh Gunna ,  Po-Yung Chang ,  Sridhar Subramanian ,  James Keller ,  Tse-Yuh Yeh

发明人： Ramesh Gunna ,  Po-Yung Chang ,  Sridhar Subramanian ,  James Keller ,  Tse-Yuh Yeh

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.

摘要翻译： 在一个实施例中，接口单元包括地址缓冲器和耦合到地址缓冲器的控制单元。 地址缓冲器被配置为存储由处理器核心产生的处理器核心请求的地址和从互连接​​收的窥探请求的地址。 所述控制单元被配置为维护多个队列，其中所述多个队列中的至少第一队列专用于窥探请求，并且所述多个队列中的至少第二队列专用于处理器核心请求。 响应于接口单元从互连接收到的第一窥探请求，控制单元被配置为分配地址缓冲器的第一地址缓冲器条目以存储第一窥探请求，并且将第一指针存储到第一地址缓冲器条目中 第一个队列。 响应于接口单元从处理器核心接收到的第一处理器核心请求，控制单元被配置为分配地址缓冲器的第二地址缓冲器条目以存储第一处理器核心请求并将第二指针存储到第二地址 第二个队列中的缓冲区条目。

公开(公告)号：US20070038791A1

公开(公告)日：2007-02-15

申请号：US11201581

申请日：2005-08-11

申请人： Sridhar Subramanian ,  James Keller ,  Ruchi Wadhawan ,  George Yiu ,  Ramesh Gunna

发明人： Sridhar Subramanian ,  James Keller ,  Ruchi Wadhawan ,  George Yiu ,  Ramesh Gunna

IPC分类号： G06F13/36

CPC分类号： G06F13/362 ,  G06F13/4022

摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US20070130410A1

公开(公告)日：2007-06-07

申请号：US11282037

申请日：2005-11-17

申请人： James Keller ,  Sridhar Subramanian ,  Ramesh Gunna

发明人： James Keller ,  Sridhar Subramanian ,  Ramesh Gunna

IPC分类号： G06F13/36

CPC分类号： G06F12/0831 ,  G06F13/362 ,  G06F13/4213 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.

摘要翻译： 接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。 在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。 控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。 控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。 在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应 。 控制单元还被配置为提供具有重试响应的第二事务的标识符。

公开(公告)号：US20070271402A1

公开(公告)日：2007-11-22

申请号：US11832841

申请日：2007-08-02

申请人： Sridhar Subramanian ,  James Keller ,  George Yiu ,  Ruchi Wadhawan

发明人： Sridhar Subramanian ,  James Keller ,  George Yiu ,  Ruchi Wadhawan

IPC分类号： G06F13/00

CPC分类号： G06F13/364 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

摘要翻译： 在各种实施例中，装置包括多个代理和互连。 在一个实施方案中，多种试剂包括第一至第四试剂。 互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还 包括在从第三代理到第四代理的第二通信路径中。 在另一实施例中，每个段由选择电路驱动。 至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。 在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。 仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

公开(公告)号：US20070038796A1

公开(公告)日：2007-02-15

申请号：US11201573

申请日：2005-08-11

申请人： Sridhar Subramanian ,  James Keller ,  George Yiu ,  Ruchi Wadhawan

发明人： Sridhar Subramanian ,  James Keller ,  George Yiu ,  Ruchi Wadhawan

IPC分类号： G06F13/00

CPC分类号： G06F13/364 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

摘要翻译： 在各种实施例中，装置包括多个代理和互连。 在一个实施方案中，多种试剂包括第一至第四试剂。 互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还 包括在从第三代理到第四代理的第二通信路径中。 在另一实施例中，每个段由选择电路驱动。 至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。 在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。 仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

公开(公告)号：US07746116B1

公开(公告)日：2010-06-29

申请号：US12356797

申请日：2009-01-21

申请人： Sridhar Narayanan ,  Chaiyasit Manovit ,  Sridhar Subramanian ,  Gerald Gras

发明人： Sridhar Narayanan ,  Chaiyasit Manovit ,  Sridhar Subramanian ,  Gerald Gras

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.

摘要翻译： 本发明的一个方面涉及一种包括第一存储元件和第一时钟门控元件的器件，其中第一存储元件的数据输入耦合到组合逻辑（CL）元件的输出，其中第一存储元件是 利用第一时钟门控元件对第一时钟门控元件进行时钟门控，以使用第一时钟使能信号来产生用于第一存储元件的时钟信号，其中产生第一时钟使能信号以在第一时钟门控元件中的每个时钟门控元件 当CL元件的至少一个控制输入中的每一个处于第一静止诱导条件时，相对于时钟信号，CL元件的至少一个数据输入处于第二静态诱导条件。

公开(公告)号：US06449759B1

公开(公告)日：2002-09-10

申请号：US09515067

申请日：2000-02-28

申请人： Mark G. Whitney ,  Sridhar Subramanian

发明人： Mark G. Whitney ,  Sridhar Subramanian

IPC分类号： G06F1750

CPC分类号： G06F17/5072 ,  G06F17/505

摘要： A computer aided design system and method for placing repeater buffers on a floor plan of an integrated circuit chip. The system includes a repeater placement tool that provides a near optimal placement of repeaters on the floor plan of a chip. The tool utilizes chip design netlist data indicating need for optimization to further decrease propagation delays in the design, wherein the data is manipulated by an algorithm which uses a combination of software programs that generate an approximate geometric placement of repeaters, that iteratively and heuristically improves the basic geometric layout, and that assigns, rule-based repeater type to each repeater, optimally determined to ensure that the strength, load, and other characteristics of the repeater buffers are correct, given the repeater location and the topology and loads of the nets.

摘要翻译： 一种用于将中继器缓冲器放置在集成电路芯片的平面图上的计算机辅助设计系统和方法。 该系统包括一个中继器放置工具，可在芯片的平面图上提供中继器的近似最佳布局。 该工具利用芯片设计网表数据，指示需要优化以进一步减少设计中的传播延迟，其中数据由使用生成中继器的近似几何位置的软件程序的组合的算法来操纵，迭代地和启发式地改进 基本几何布局，并且为每个中继器分配基于规则的中继器类型，最佳确定，以确保中继器缓冲器的强度，负载和其他特性是正确的，给定中继器位置和网络的拓扑和负载。

公开(公告)号：US08503264B1

公开(公告)日：2013-08-06

申请号：US13300512

申请日：2011-11-18

申请人： Sridhar Narayanan ,  Sridhar Subramanian ,  Matthew H. Klein ,  Patrick J. Crotty

发明人： Sridhar Narayanan ,  Sridhar Subramanian ,  Matthew H. Klein ,  Patrick J. Crotty

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.

摘要翻译： 存储器结构可以包括第一存储器块，其包括对应于地址范围的地址的第一子集的多个存储器单元和包括对应于地址范围的地址的第二子集的多个存储器单元的第二存储器块 。 存储器结构可以包括耦合到第一存储器块和第二存储器块并被配置为向第一存储器块和第二存储器块提供控制信号的控制电路。 第一存储器块和第二存储器块可以被配置为响应于控制信号彼此独立地实现降低功率模式。

公开(公告)号：US08099703B1

公开(公告)日：2012-01-17

申请号：US12325976

申请日：2008-12-01

申请人： Chaiyasit Manovit ,  Sridhar Narayanan ,  Sridhar Subramanian

发明人： Chaiyasit Manovit ,  Sridhar Narayanan ,  Sridhar Subramanian

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504 ,  G06F2217/78

摘要： Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications. The equivalency between the golden design and the power optimized design can then be verified by checking the golden design and the first design transformation, and then by checking between each pair of the plurality of intermediate design transformations, and finally by checking the last design transformation and the power optimized design.

摘要翻译： 本发明的实施例提供了使用组合等价性检查来验证功率优化设计的功能等同性及其原始的，未优化的设计（称为黄金设计）的方法和系统。 由于一些固有的限制，使得组合等价检查器不能在单个步骤中证明两个设计的等同性，引入了一系列中间设计变换。 这些变换取决于从黄金设计生成功率优化设计中使用的技术，并且可以以提供必要结构来指定整套有效结构修改的变换语言一般性地描述。 然后通过检查黄金设计和第一次设计变换，然后通过检查每对多个中间设计变换之间的检验，最后通过检查最后的设计变换和 电源优化设计。

公开(公告)号：US06624681B1

公开(公告)日：2003-09-23

申请号：US09918209

申请日：2001-07-30

申请人： Bruce A. Loyer ,  Sridhar Subramanian ,  Michael S. Quimby ,  Niranjan Venigandla

发明人： Bruce A. Loyer ,  Sridhar Subramanian ,  Michael S. Quimby ,  Niranjan Venigandla

IPC分类号： G06F104

CPC分类号： G06F1/3237 ,  G06F1/10 ,  G06F1/3203 ,  Y02D10/128

摘要： A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.

摘要翻译： 一种用于在保持PLL锁定的同时停止时钟树的电路和方法。 时钟电路包括锁定环路电路和时钟树分配网络。 锁定环电路接收输入时钟信号，并根据反馈信号产生PLL输出时钟。 时钟树耦合到锁定环电路，并将PLL输出时钟传送到多个时钟电路元件。 时钟电路还包括门控电路和反馈延迟电路。 门控电路耦合在时钟树分配网络的锁定环路电路之间，并选择性地禁止PLL输出时钟计时时钟树分配网络。 反馈延迟电路在操作期间提供反馈信号，其表示PLL输出时钟的延迟版本，包括当门控电路禁止PLL输出时钟计时时钟树时。