公开(公告)号：US08804885B2

公开(公告)日：2014-08-12

申请号：US11311003

申请日：2005-12-19

申请人： Rami Banna ,  Adriel P. Kind ,  Tomasz Prokop ,  Dominic W. Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Adriel P. Kind ,  Tomasz Prokop ,  Dominic W. Yip ,  Gongyu Zhou

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04B1/7101

摘要： A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

摘要翻译： 在一个实施例中，多级接收机包括一系列处理级。 至少一个处理级包括第一处理块，延迟块和第二处理块。 第一处理块适于接收输入信号并从输入信号生成一个或多个处理参数。 延迟块适于产生延迟信号。 第二处理块适于将一个或多个处理参数应用于延迟信号以产生输出信号。 延迟块补偿与第一处理块生成一个或多个处理参数相关联的一个或多个处理延迟。

公开(公告)号：US08654904B2

公开(公告)日：2014-02-18

申请号：US11869394

申请日：2007-10-09

申请人： Uwe Sontowski ,  Dominic W. Yip

发明人： Uwe Sontowski ,  Dominic W. Yip

IPC分类号： H03H7/40 ,  H04L27/06

CPC分类号： H04L25/03019 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03496 ,  H04L2025/03617

摘要： In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating.

摘要翻译： 在一个实施例中，接收机包括自动增益控制器（AGC），均衡器，控制器和寄存器接口。 AGC进行增益调整以补偿接收信号的平均幅度的变化。 均衡器具有计算系数的系数更新器和将系数应用于接收信号以产生均衡信号的有限脉冲响应（FIR）滤波器。 在AGC的增益调整期间，寄存器接口向系数更新器提供加权冻结信号，随后系统更新器将冻结系统的冻结持续时间周期的更新。 然后，寄存器接口根据增益调整的大小向系数更新器提供由控制器生成的缩放因子。 在冻结期结束时，系数更新器对系数应用缩放因子，解冻系数更新。

公开(公告)号：US20090092181A1

公开(公告)日：2009-04-09

申请号：US11869394

申请日：2007-10-09

申请人： Uwe Sontowski ,  Dominic W. Yip

发明人： Uwe Sontowski ,  Dominic W. Yip

IPC分类号： H03H7/30

CPC分类号： H04L25/03019 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03496 ,  H04L2025/03617

摘要： In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating.

摘要翻译： 在一个实施例中，接收机包括自动增益控制器（AGC），均衡器，控制器和寄存器接口。 AGC进行增益调整以补偿接收信号的平均幅度的变化。 均衡器具有计算系数的系数更新器和将系数应用于接收信号以产生均衡信号的有限脉冲响应（FIR）滤波器。 在AGC的增益调整期间，寄存器接口向系数更新器提供加权冻结信号，随后系统更新器将冻结系统的冻结持续时间周期的更新。 然后，寄存器接口根据增益调整的大小向系数更新器提供由控制器生成的缩放因子。 在冻结期结束时，系数更新器将比例因子应用于系数，并解冻系数更新。