公开(公告)号：US08582635B2

公开(公告)日：2013-11-12

申请号：US13410473

申请日：2012-03-02

申请人： Tomasz Prokop ,  Chaitanya Palusa

发明人： Tomasz Prokop ,  Chaitanya Palusa

IPC分类号： H03H7/30

CPC分类号： H04L25/03044

摘要： In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

摘要翻译： 在所描述的实施例中，浮动分接头，前馈均衡器（FT-FFE）在均衡例如SerDes接收机中的有线线路信道时实现与全尺寸长FFE相当的性能。 FT-FFE可以用作独立的数据路径均衡器，或者可以与其他均衡技术结合使用。

公开(公告)号：US20130243066A1

公开(公告)日：2013-09-19

申请号：US13419009

申请日：2012-03-13

申请人： Chaitanya Palusa ,  Tomasz Prokop ,  Adam B. Healey ,  Ye Liu

发明人： Chaitanya Palusa ,  Tomasz Prokop ,  Adam B. Healey ,  Ye Liu

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  H04L27/02

摘要： In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

摘要翻译： 在所描述的实施例中，决策前馈均衡器（DFFE）包括组合前馈均衡器（FFE）和判决反馈均衡器（DFE）的特征的混合架构。 一个示例性的DFFE提供了比单独的FFE实现相对改进的噪声和串扰抗扰度，并且相比于单独的DFE实现相对较低的突发错误传播。 与仅DFE实现相比，示例性DFFE是相对简单的实现，因为很少或没有关键的反馈路径。 示例性DFFE允许其DFE元件的并行实现，而对于较高数量的抽头，硬件的指数增加。 示例性DFFE允许级联，允许在相对低的实施成本下逐渐改进BER，作为实现多抽头DFE性能的解决方案。

公开(公告)号：US20070064590A1

公开(公告)日：2007-03-22

申请号：US11209421

申请日：2005-08-23

申请人： Tomasz Prokop ,  Gongyu Zhou

发明人： Tomasz Prokop ,  Gongyu Zhou

IPC分类号： H04J11/00

CPC分类号： H04L27/2662 ,  H04J13/0044 ,  H04J13/12

摘要： A method of generating a code sequence comprises populating at least one buffer with initial values based on a received spreading factor and desired code index; receiving a timing strobe; changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and outputting at least one code sequence value based on the values in the at least one buffer. An apparatus for generating a code sequence comprises means for populating at least one buffer with initial values based on a received spreading factor and desired code index; means for receiving a timing strobe; means for changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and means for outputting at least one code sequence value based on the values in the at least one buffer.

摘要翻译： 一种生成代码序列的方法，包括基于接收到的扩展因子和期望的代码索引填充具有初始值的至少一个缓冲器; 接收定时频闪; 基于独立于与定时选通相关联的任何计数值的算法，在接收到定时选通信号时改变至少一个缓冲器中的值; 以及基于所述至少一个缓冲器中的值输出至少一个代码序列值。 一种用于生成代码序列的装置，包括：用于根据所接收的扩展因子和期望代码索引，填充具有初始值的至少一个缓冲器的装置; 用于接收定时选通的装置; 用于在基于与所述定时选通相关联的任何计数值独立的算法接收到定时选通时改变所述至少一个缓冲器中的值的装置; 以及用于基于所述至少一个缓冲器中的值输出至少一个代码序列值的装置。

公开(公告)号：US08787439B2

公开(公告)日：2014-07-22

申请号：US13419009

申请日：2012-03-13

申请人： Chaitanya Palusa ,  Tomasz Prokop ,  Adam B. Healey ,  Ye Liu

发明人： Chaitanya Palusa ,  Tomasz Prokop ,  Adam B. Healey ,  Ye Liu

IPC分类号： H04L27/22

CPC分类号： H04L25/03057 ,  H04L27/02

摘要： In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

摘要翻译： 在所描述的实施例中，决策前馈均衡器（DFFE）包括组合前馈均衡器（FFE）和判决反馈均衡器（DFE）的特征的混合架构。 一个示例性的DFFE提供了比单独的FFE实现相对改进的噪声和串扰抗扰度，并且相比于单独的DFE实现相对较低的突发错误传播。 与仅DFE实现相比，示例性DFFE是相对简单的实现，因为很少或没有关键的反馈路径。 示例性DFFE允许其DFE元件的并行实现，而对于较高数量的抽头，硬件的指数增加。 示例性DFFE允许级联，允许在相对低的实施成本下逐渐改进BER，作为实现多抽头DFE性能的解决方案。

公开(公告)号：US08462614B2

公开(公告)日：2013-06-11

申请号：US13009044

申请日：2011-01-19

申请人： Tomasz Prokop ,  Gongyu Zhou

发明人： Tomasz Prokop ,  Gongyu Zhou

IPC分类号： H04J11/00 ,  H04L27/26

CPC分类号： H04L27/2662 ,  H04J13/0044 ,  H04J13/12

摘要： In one embodiment, a buffer-based method for generating codes (such as Orthogonal Variable Spreading Factor (OVSF) codes) for spreading and despreading data, without using a chip-rate counter. First, a buffer is populated with initial values based on a received spreading factor and desired code index. Next, a timing strobe is received, and the values in the buffer are changed upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe. Finally, a code sequence value is generated based on the values in the buffer.

摘要翻译： 在一个实施例中，用于生成用于扩展和解扩数据的代码（诸如正交可变扩频因子（OVSF）码）的基于缓冲器的方法，而不使用码片速率计数器。 首先，基于接收到的扩频因子和期望的码索引来填充初始值的缓冲器。 接下来，接收到定时选通脉冲，并且基于与与定时选通相关联的任何计数值独立的算法接收到定时选通时，缓冲器中的值被改变。 最后，根据缓冲区中的值生成代码序列值。

公开(公告)号：US20130230092A1

公开(公告)日：2013-09-05

申请号：US13410473

申请日：2012-03-02

申请人： Tomasz Prokop ,  Chaitanya Palusa

发明人： Tomasz Prokop ,  Chaitanya Palusa

IPC分类号： H04L27/01

CPC分类号： H04L25/03044

摘要： In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

摘要翻译： 在所描述的实施例中，浮动分接头，前馈均衡器（FT-FFE）在均衡例如SerDes接收机中的有线线路信道时实现与全尺寸长FFE相当的性能。 FT-FFE可以用作独立的数据路径均衡器，或者可以与其他均衡技术结合使用。

公开(公告)号：US07894327B2

公开(公告)日：2011-02-22

申请号：US11209421

申请日：2005-08-23

申请人： Tomasz Prokop ,  Gongyu Zhou

发明人： Tomasz Prokop ,  Gongyu Zhou

IPC分类号： H04B7/216

CPC分类号： H04L27/2662 ,  H04J13/0044 ,  H04J13/12

摘要： A method of generating a code sequence comprises populating at least one buffer with initial values based on a received spreading factor and desired code index; receiving a timing strobe; changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and outputting at least one code sequence value based on the values in the at least one buffer. An apparatus for generating a code sequence comprises means for populating at least one buffer with initial values based on a received spreading factor and desired code index; means for receiving a timing strobe; means for changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and means for outputting at least one code sequence value based on the values in the at least one buffer.

摘要翻译： 一种生成代码序列的方法，包括基于接收到的扩展因子和期望的代码索引填充具有初始值的至少一个缓冲器; 接收定时频闪; 基于独立于与定时选通相关联的任何计数值的算法，在接收到定时选通信号时改变至少一个缓冲器中的值; 以及基于所述至少一个缓冲器中的值输出至少一个代码序列值。 一种用于生成代码序列的装置，包括：用于根据所接收的扩展因子和期望代码索引，填充具有初始值的至少一个缓冲器的装置; 用于接收定时选通的装置; 用于在基于与所述定时选通相关联的任何计数值独立的算法接收到定时选通时改变所述至少一个缓冲器中的值的装置; 以及用于基于所述至少一个缓冲器中的值输出至少一个代码序列值的装置。

公开(公告)号：US20070147560A1

公开(公告)日：2007-06-28

申请号：US11318812

申请日：2005-12-27

申请人： Rami Banna ,  Tomasz Prokop ,  Long Ung ,  Dominic Yip

发明人： Rami Banna ,  Tomasz Prokop ,  Long Ung ,  Dominic Yip

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03611

摘要： A communications circuit includes a filter module with a sampling window, a control module, and an input buffer. The control module has a ray parameter interface to obtain information regarding significant ray changes that make it desirable to re-position the sampling window. The control module determines re-positioning parameters, responsive to this information, which reflect the re-positioning of the sampling window. The input buffer obtains samples of a received signal and outputs received signal data to the filter module. The filter module obtains the re-positioning parameters from the control module, and the filter module and control module temporally re-position the sampling window in duration and/or location in accordance with the re-positioning parameters, and output a filtered chip.

摘要翻译： 通信电路包括具有采样窗口的滤波器模块，控制模块和输入缓冲器。 控制模块具有射线参数界面，以获得关于重要射线变化的信息，这使得需要重新定位采样窗口。 响应于该信息，控制模块确定重新定位参数，其反映采样窗口的重新定位。 输入缓冲器获得接收信号的样本，并将接收的信号数据输出到滤波器模块。 滤波器模块从控制模块获得重定位参数，滤波器模块和控制模块根据重定位参数在持续时间和/或位置暂时重新定位采样窗口，并输出滤波芯片。

公开(公告)号：US20060233229A1

公开(公告)日：2006-10-19

申请号：US11107049

申请日：2005-04-15

申请人： Christopher Nicol ,  Tomasz Prokop ,  Dominic Yip

发明人： Christopher Nicol ,  Tomasz Prokop ,  Dominic Yip

IPC分类号： H03K5/159 ,  H04B1/00 ,  H04L1/02

CPC分类号： H04B7/0845 ,  H04B7/0857 ,  H04B7/0871 ,  H04B7/0874 ,  H04B7/0891 ,  Y02D70/1242 ,  Y02D70/444

摘要： A communications circuit can operate in a first mode, such as a diversity mode including space time transmit diversity (STTD). In this mode, a number of equalizer filter portions connected to a number of post-equalizer processors are employed. When the diversity mode is not required, the extra equalizer filter portions would represent a waste of power consumption and/or chip space. A combining circuit and suitable control circuitry are provided to allow use of the additional equalizer filter portions to be made in other operating modes. Appropriate trade-offs can be made based on power consumption and performance.

公开(公告)号：US08804885B2

公开(公告)日：2014-08-12

申请号：US11311003

申请日：2005-12-19

申请人： Rami Banna ,  Adriel P. Kind ,  Tomasz Prokop ,  Dominic W. Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Adriel P. Kind ,  Tomasz Prokop ,  Dominic W. Yip ,  Gongyu Zhou

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04B1/7101

摘要： A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

摘要翻译： 在一个实施例中，多级接收机包括一系列处理级。 至少一个处理级包括第一处理块，延迟块和第二处理块。 第一处理块适于接收输入信号并从输入信号生成一个或多个处理参数。 延迟块适于产生延迟信号。 第二处理块适于将一个或多个处理参数应用于延迟信号以产生输出信号。 延迟块补偿与第一处理块生成一个或多个处理参数相关联的一个或多个处理延迟。