公开(公告)号：US20090092181A1

公开(公告)日：2009-04-09

申请号：US11869394

申请日：2007-10-09

申请人： Uwe Sontowski ,  Dominic W. Yip

发明人： Uwe Sontowski ,  Dominic W. Yip

IPC分类号： H03H7/30

CPC分类号： H04L25/03019 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03496 ,  H04L2025/03617

摘要： In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating.

摘要翻译： 在一个实施例中，接收机包括自动增益控制器（AGC），均衡器，控制器和寄存器接口。 AGC进行增益调整以补偿接收信号的平均幅度的变化。 均衡器具有计算系数的系数更新器和将系数应用于接收信号以产生均衡信号的有限脉冲响应（FIR）滤波器。 在AGC的增益调整期间，寄存器接口向系数更新器提供加权冻结信号，随后系统更新器将冻结系统的冻结持续时间周期的更新。 然后，寄存器接口根据增益调整的大小向系数更新器提供由控制器生成的缩放因子。 在冻结期结束时，系数更新器将比例因子应用于系数，并解冻系数更新。

公开(公告)号：US20120076194A1

公开(公告)日：2012-03-29

申请号：US13311654

申请日：2011-12-06

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

IPC分类号： H04L27/01

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US20090080506A1

公开(公告)日：2009-03-26

申请号：US12158388

申请日：2007-01-10

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

IPC分类号： H04L27/01

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US07555071B2

公开(公告)日：2009-06-30

申请号：US11239274

申请日：2005-09-29

申请人： Uwe Sontowski

发明人： Uwe Sontowski

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H03M13/29 ,  H03M13/47 ,  H03M13/6306 ,  H03M13/6368 ,  H03M13/658 ,  H04L1/0054 ,  H04L1/0066

摘要： Methods and apparatus are provided for non-linear scaling of log likelihood ratio (LLR) values in a decoder. A decoder according to the present invention processes a received signal by generating a plurality of log-likelihood ratios having a first resolution; applying a non-linear function to the plurality of log-likelihood ratios to generate a plurality of log-likelihood ratios having a lower resolution; and applying the plurality of log-likelihood ratios having a lower resolution to a decoder. The non-linear function can distribute the log-likelihood ratios, for example, such that the frequency of each LLR value is more uniform than a linear scaling.

摘要翻译： 为解码器中对数似然比（LLR）值的非线性缩放提供了方法和装置。 根据本发明的解码器通过产生具有第一分辨率的多个对数似然比来处理接收信号; 对所述多个对数似然比应用非线性函数以产生具有较低分辨率的多个对数似然比; 以及将具有较低分辨率的所述多个对数似然比应用于解码器。 非线性函数可以分布对数似然比，例如，使得每个LLR值的频率比线性缩放更均匀。

公开(公告)号：US08462839B2

公开(公告)日：2013-06-11

申请号：US13311654

申请日：2011-12-06

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme K. Woodward

IPC分类号： H03H7/30

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US08098723B2

公开(公告)日：2012-01-17

申请号：US12158388

申请日：2007-01-10

申请人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme Woodward

发明人： Rami Banna ,  Uwe Sontowski ,  Long Ung ,  Graeme Woodward

IPC分类号： H03H7/30

CPC分类号： H04L25/03044 ,  H04B1/7097 ,  H04L2025/03509 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

摘要翻译： 在一个实施例中，接收器具有参考发生器和主均衡器。 参考发生器使用一个或多个导频参考信号来均衡接收信号。 然后，基准发生器解码均衡信号的一个或多个预定数据信道，对每个解码信道的数据作出硬判决，并重新生成每个解码信道的原始编码序列。 主均衡器使用每个重编码信道作为附加参考信号以及一个或多个导频信号来均衡接收信号的时间延迟版本。 在替代实施例中，接收机还可以具有步长生成器，其基于重新编码的信道的数量和这些信道的功率从查找表中选择最佳步长。 然后，主均衡器与重新编码的信道一起使用步长来均衡时间延迟的接收信号。

公开(公告)号：US20090296798A1

公开(公告)日：2009-12-03

申请号：US12295683

申请日：2007-04-05

申请人： Rami Banna ,  Mark A. Bickerstaff ,  Matthew E. Cooke ,  Adriel P. kind ,  Yi-Chen Li ,  Oliver Ridler ,  Uwe Sontowski ,  Charles N. A. Thomas ,  Long Ung ,  Koen Van den Beld ,  Benjamin J. Widdup ,  Graeme K. Woodward ,  Dominic Wing-Kin Yip ,  Gongyu Zhou

发明人： Rami Banna ,  Mark A. Bickerstaff ,  Matthew E. Cooke ,  Adriel P. kind ,  Yi-Chen Li ,  Oliver Ridler ,  Uwe Sontowski ,  Charles N. A. Thomas ,  Long Ung ,  Koen Van den Beld ,  Benjamin J. Widdup ,  Graeme K. Woodward ,  Dominic Wing-Kin Yip ,  Gongyu Zhou

IPC分类号： H03H7/40 ,  H04W4/00

CPC分类号： H04B1/70754 ,  H04B1/7097 ,  H04B2201/70701 ,  H04L25/03057 ,  H04L25/03292 ,  H04L2025/03617 ,  H04L2025/03687

摘要： In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.

摘要翻译： 在一个实施例中，用于3GPP版本6类别（7.2Mb / s）HSDPA的HSDPA协处理器为90nm CMOS中的HSDPA提供所有芯片速率，符号速率，物理信道和传输信道处理。 协处理器设计可扩展到高达14 Mb / s的所有HSDPA数据速率。 协处理器基于NLMS均衡器实现高级接收机，支持RX分集和TX分集，并且比典型的单天线耙式接收机提供高达6.4 dB的性能。 因此，3GPP R6 HSDPA功能可以以合理的增量成本和功率被添加到与本发明实施例一致的HSDPA协处理器的传统R99调制解调器。

公开(公告)号：US08654904B2

公开(公告)日：2014-02-18

申请号：US11869394

申请日：2007-10-09

申请人： Uwe Sontowski ,  Dominic W. Yip

发明人： Uwe Sontowski ,  Dominic W. Yip

IPC分类号： H03H7/40 ,  H04L27/06

CPC分类号： H04L25/03019 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03496 ,  H04L2025/03617

摘要： In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating.

摘要翻译： 在一个实施例中，接收机包括自动增益控制器（AGC），均衡器，控制器和寄存器接口。 AGC进行增益调整以补偿接收信号的平均幅度的变化。 均衡器具有计算系数的系数更新器和将系数应用于接收信号以产生均衡信号的有限脉冲响应（FIR）滤波器。 在AGC的增益调整期间，寄存器接口向系数更新器提供加权冻结信号，随后系统更新器将冻结系统的冻结持续时间周期的更新。 然后，寄存器接口根据增益调整的大小向系数更新器提供由控制器生成的缩放因子。 在冻结期结束时，系数更新器对系数应用缩放因子，解冻系数更新。

公开(公告)号：US20080075159A1

公开(公告)日：2008-03-27

申请号：US11731173

申请日：2007-03-30

申请人： Uwe Sontowski ,  Graeme K. Woodward

发明人： Uwe Sontowski ,  Graeme K. Woodward

IPC分类号： H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03038 ,  H03H21/0012 ,  H03H2021/0092 ,  H04L2025/03617

摘要： In one embodiment, a receiver has a main equalizer and an auxiliary equalizer. The auxiliary equalizer equalizes a received signal using adaptively generated sets of auxiliary filter coefficients. Each set is generated by 1) filtering a received signal to generate an equalized signal, 2) calculating an error based on the equalized signal, and 3) calculating the set of coefficients based on the error and the prior set of auxiliary filter coefficients. The main equalizer equalizes a delayed version of the input signal by first applying a set of auxiliary filter coefficients, copied from the auxiliary equalizer, to the delayed version. Then, the main equalizer continues to equalize the delayed signal using main filter coefficients that are adaptively generated in a manner analogous to that of the auxiliary equalizer. In other embodiments, the number of sets of auxiliary filter coefficients and the period in which the sets are copied may vary.

摘要翻译： 在一个实施例中，接收器具有主均衡器和辅助均衡器。 辅助均衡器使用自适应生成的辅助滤波器系数组来均衡接收信号。 每个集合通过以下方式产生：1）对接收到的信号进行滤波以产生均衡信号，2）基于均衡信号计算误差，以及3）基于误差和先前的辅助滤波器系数集计算系数集合。 主均衡器通过首先将从辅助均衡器复制的一组辅助滤波器系数应用到延迟版本来均衡延迟版本的输入信号。 然后，主均衡器继续使用以类似于辅助均衡器的方式自适应地产生的主滤波器系数来均衡延迟信号。 在其他实施例中，辅助滤波器系数的集合数和集合被复制的周期可以变化。

公开(公告)号：US20070071140A1

公开(公告)日：2007-03-29

申请号：US11239274

申请日：2005-09-29

申请人： Uwe Sontowski

发明人： Uwe Sontowski

IPC分类号： H03D1/00

CPC分类号： H03M13/29 ,  H03M13/47 ,  H03M13/6306 ,  H03M13/6368 ,  H03M13/658 ,  H04L1/0054 ,  H04L1/0066

摘要： Methods and apparatus are provided for non-linear scaling of log likelihood ratio (LLR) values in a decoder. A decoder according to the present invention processes a received signal by generating a plurality of log-likelihood ratios having a first resolution; applying a non-linear function to the plurality of log-likelihood ratios to generate a plurality of log-likelihood ratios having a lower resolution; and applying the plurality of log-likelihood ratios having a lower resolution to a decoder. The non-linear function can distribute the log-likelihood ratios, for example, such that the frequency of each LLR value is more uniform than a linear scaling.

摘要翻译： 为解码器中对数似然比（LLR）值的非线性缩放提供了方法和装置。 根据本发明的解码器通过产生具有第一分辨率的多个对数似然比来处理接收信号; 对所述多个对数似然比应用非线性函数以产生具有较低分辨率的多个对数似然比; 以及将具有较低分辨率的所述多个对数似然比应用于解码器。 非线性函数可以分布对数似然比，例如，使得每个LLR值的频率比线性缩放更均匀。