公开(公告)号：US06606680B2

公开(公告)日：2003-08-12

申请号：US09895224

申请日：2001-06-29

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1202

CPC分类号： G06F12/0897 ,  G11C7/22 ,  G11C11/408 ,  G11C2207/104

摘要： An apparatus for accessing a banked embedded dynamic random access memory device is disclosed. The apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.

摘要翻译： 公开了一种用于访问嵌入式动态随机存取存储器件的装置。 用于访问堆叠式嵌入式动态随机存取存储器（DRAM）装置的装置包括通用功能控制逻辑和银行RAS控制器。 一般的功能控制逻辑耦合到组合的嵌入式DRAM设备的每个组。 耦合到一般功能控制逻辑，银行RAS控制器包括具有多个位的旋转移位寄存器。 旋转移位寄存器内的每个位对应于组合嵌入式DRAM器件的每一组。 这样，旋转移位寄存器的一位内的第一值允许访问分组的嵌入式DRAM设备的相关联的存储体，并且旋转移位寄存器的一位内的第二值拒绝对相关联的组的嵌入式DRAM 设备。

公开(公告)号：US06574719B2

公开(公告)日：2003-06-03

申请号：US09903720

申请日：2001-07-12

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F13/28 ,  G06F13/4243

摘要： An apparatus for providing concurrent communications between multiple memory devices and a processor is disclosed. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block. The receiver that had received the occurrence of a cycle adjustment informs the other receivers that did not receive the occurrence of a cycle adjustment to use their cycle delay block to delay the incoming data for at least one cycle.

摘要翻译： 公开了一种用于在多个存储器件和处理器之间提供并发通信的装置。 每个存储器件包括驱动器，相位/周期调整感测电路和总线对准通信逻辑。 每个相位/周期调整感测电路检测来自存储器件内相应的驱动器的周期调整的发生。 如果已经检测到循环调整的发生，则总线对准通信逻辑将处理器的循环调整的发生传达给处理器。 总线对准通信逻辑还将循环调整的发生与其他存储器件中的总线对准通信逻辑进行通信。 处理器内有多个接收器，并且每个接收器被设计成从存储器设备中的相应驱动器接收数据。 每个接收器包括循环延迟块。 接收到发生循环调整的接收器通知其他接收机没有接收周期调整的发生，以使用它们的周期延迟块来延迟输入数据至少一个周期。

公开(公告)号：US06678814B2

公开(公告)日：2004-01-13

申请号：US09895225

申请日：2001-06-29

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1202

CPC分类号： G06F12/0223 ,  G06F9/5016

摘要： An apparatus for allocating data usage in an embedded dynamic random access memory (DRAM) device is disclosed. The apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.

摘要翻译： 公开了一种用于在嵌入式动态随机存取存储器（DRAM）装置中分配数据使用的装置。 用于在嵌入式动态随机存取存储器（DRAM）装置内分配数据用途的装置包括控制分析电路，数据/命令流电路和分区管理控制。 控制分析电路根据处理器的处理性能生成分配信号。 耦合到嵌入式DRAM设备，数据/命令流程电路控制从处理器到嵌入式DRAM设备的数据流。 耦合到控制分析电路的分区管理控制将嵌入式DRAM设备分割成第一分区和第二分区。 存储在第一分区中的数据根据​​它们各自的用途而不同于存储在第二分区中的数据。 通过来自控制分析电路的分配信号动态分配第一和第二分区的分配百分比。

公开(公告)号：US06467030B1

公开(公告)日：2002-10-15

申请号：US09435962

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

IPC分类号： G06F1200

CPC分类号： G06F12/0897 ,  G06F12/0862 ,  G06F2212/6022

摘要： A method and apparatus for forwarding data in a hierarchial cache memory architecture is disclosed. A cache memory hierarchy includes multiple levels of cache memories, each level having a different size and speed. A command is initially issued from a processor to the cache memory hierarchy. If the command is a Demand Load command, data corresponding to the Demand Load command is immediately forwarded from a cache having the data to the processor. Otherwise, if the command is a Prefetch Load command, data corresponding to the Prefetch Load command is held in a cache reload buffer within a cache memory preceding the processor.

摘要翻译： 公开了一种用于在分级高速缓冲存储器架构中转发数据的方法和装置。 高速缓冲存储器层级包括多级缓存存储器，每级具有不同的大小和速度。 命令最初从处理器发出到高速缓存存储器层次结构。 如果命令是Demand Load命令，则与Demand Load命令相对应的数据将立即从具有数据的缓存转发到处理器。 否则，如果命令是预取加载命令，则与预取加载命令对应的数据保存在处理器之前的高速缓存中的缓存重新加载缓冲区中。

公开(公告)号：US06553463B1

公开(公告)日：2003-04-22

申请号：US09436959

申请日：1999-11-09

申请人： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

发明人： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

IPC分类号： G06F1200

CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/6082

摘要： A method and system for high speed data access of a banked cache memory. In accordance with the method and system of the present invention, during a first cycle, in response to receipt of a request address at an access controller, the request address is speculatively transmitted to a banked cache memory, where the speculative transmission has at least one cycle of latency. Concurrently, the request address is snooped in a directory associated with the banked cache memory. Thereafter, during a second cycle the speculatively transmitted request address is distributed to each of multiple banks of memory within the banked cache memory. In addition, the banked cache memory is provided with a bank indication indicating which bank of memory among the multiple banks of memory contains the request address, in response to a bank hit from snooping the directory. Thereafter, data associated with the request address is output from the banked cache memory, in response to the bank indication, such that access time to a high latency remote banked cache memory is minimized.

摘要翻译： 一种用于高速缓存存储器的高速数据访问的方法和系统。 根据本发明的方法和系统，在第一周期期间，响应于在访问控制器处接收到请求地址，请求地址被推测地发送到存储的高速缓冲存储器，其中推测传输具有至少一个 延迟周期。 同时，请求地址被窥探在与存储的高速缓冲存储器相关联的目录中。 此后，在第二周期期间，推测性发送的请求地址被分配到分组缓存存储器内的多个存储器组中的每一个。 此外，为了响应于窥探目录的银行命中，所述存储体高速缓存存储器具有指示多个存储器组中的存储器组包含请求地址的存储体指示。 此后，响应于存储体指示，从存储的高速缓冲存储器输出与请求地址相关联的数据，使得到高等待时间的远程分组高速缓冲存储器的访问时间被最小化。

公开(公告)号：US06298416B1

公开(公告)日：2001-10-02

申请号：US09437040

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

IPC分类号： G06F1208

CPC分类号： G06F12/0897

摘要： A method and apparatus for transmitting control signals within a hierarchial cache memory architecture of a data processing system is disclosed. The cache memory hierarchy includes multiple levels of cache memories, each level may have a different size and speed. In response to a processor request for information, a control command is sent to the cache memory hierarchy. The control command includes multiple control blocks. Beginning at the lowest possible cache level of the cache memory hierarchy, a determination is made whether or not there is a cache hit at a current level of the cache memory hierarchy. In response to a determination that there is not a cache hit at the current level, an abbreviated control command is sent to an upper cache level of the cache memory hierarchy, after a control block that corresponds to the current level is removed from the control command.

摘要翻译： 公开了一种用于在数据处理系统的分级高速缓冲存储器架构内发送控制信号的方法和装置。 高速缓存存储器层次结构包括多级缓存存储器，每个级别可以具有不同的大小和速度。 响应于处理器对信息的请求，控制命令被发送到高速缓冲存储器层次结构。 控制命令包括多个控制块。 从高速缓存存储器层次结构的最低可能缓存级开始，确定高速缓存存储器层级的当前级别是否存在高速缓存命中。 响应于在当前级别没有高速缓存命中的确定，在对应于当前级别的控制块从控制命令中移除之后，将缩写控制命令发送到高速缓存存储器层次结构的高级缓存级别 。

公开(公告)号：US06546469B2

公开(公告)日：2003-04-08

申请号：US09749328

申请日：2001-03-12

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Guy Lynn Guthrie ,  Jody B. Joyner

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Guy Lynn Guthrie ,  Jody B. Joyner

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized. The invention is not limited to any particular type of instruction, and the synchronization functionality may be hardware or software programmable.

公开(公告)号：US06442653B1

公开(公告)日：2002-08-27

申请号：US09339403

申请日：1999-06-24

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

IPC分类号： G06F1200

CPC分类号： G06F12/0815 ,  G06F12/127 ,  G06F2212/2542

摘要： A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes data storage and a plurality of latency indicators that each indicate an access latency to the distributed memory for associated data stored in the data storage. As a result, transactions related to cached data can be efficiently routed and addressed and efficient victim selection and deallocation policies can be implemented in the cache.

摘要翻译： 数据处理系统包括处理单元，包括本地存储器的分布式存储器和具有不同访问延迟的远程存储器，以及耦合到处理单元和分布式存储器的高速缓存。 高速缓存包括数据存储器和多个等待时间指示器，每个等待时间指示器指示分配的存储器对存储在数据存储器中的相关数据的访问等待时间。 因此，可以有效地路由和寻址与缓存数据相关的事务，并且可以在缓存中实现有效的牺牲者选择和释放策略。

公开(公告)号：US06397303B1

公开(公告)日：2002-05-28

申请号：US09339408

申请日：1999-06-24

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

IPC分类号： G06F1200

CPC分类号： G06F12/0811

摘要： A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple granules of data and a number of state fields associated with the granules of data. Each state field has a plurality of possible states including an O state indicating that an associated granule is consistent with corresponding data in the memory and has unknown coherency with respect to peer caches in the data processing system. Thus, a cache is permitted to store memory-consistent, but possibly non-coherent data in order to offer processing units in the data processing system lower latency to an image of system memory.

摘要翻译： 多处理器数据处理系统包括互连，耦合到互连的多个处理单元以及耦合到多个处理单元的至少一个系统存储器和多个高速缓存。 适用于这种数据处理系统的高速缓存包括包含多个数据颗粒和与数据颗粒相关联的多个状态字段的数据存储。 每个状态字段具有多个可能状态，包括指示相关联的粒子与存储器中的对应数据一致的O状态，并且与数据处理系统中的对等高速缓存具有未知的一致性。 因此，缓存被允许存储内存一致但可能非相干的数据，以便为数据处理系统中的处理单元提供对系统存储器的图像的较低延迟。

公开(公告)号：US06356982B1

公开(公告)日：2002-03-12

申请号：US09339405

申请日：1999-06-24

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai

IPC分类号： G06F1200

CPC分类号： G06F12/0831 ,  G06F12/0862

摘要： A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing a data granule, a state field associated with the data granule, and a cache controller. The state field has a plurality of possible states including a first state that indicates that the data granule is consistent with corresponding data in the memory and has unknown coherency with respect to other peer caches among the plurality of caches. To update the state of the data granule from the first state, the cache controller issues on the interconnect a transaction specifying an address associated with the data granule. In response to receipt of a combined response of the plurality of caches, the cache controller updates the state field to a second state among the plurality of possible states.

摘要翻译： 多处理器数据处理系统包括互连，耦合到互连的多个处理单元以及耦合到多个处理单元的至少一个系统存储器和多个高速缓存。 适用于这种数据处理系统的缓存包括包含数据粒子的数据存储器，与数据粒子相关联的状态字段以及高速缓存控制器。 状态字段具有多个可能状态，包括指示数据粒子与存储器中的相应数据一致的第一状态，并且在多个高速缓存中相对于其他对等体高速缓存具有未知的一致性。 为了从第一状态更新数据粒子的状态，高速缓存控制器在互连器上发出指定与数据粒子相关联的地址的事务。 响应于接收到多个高速缓存的组合响应，高速缓存控制器将状态字段更新为多个可能状态中的第二状态。