公开(公告)号：US06865695B2

公开(公告)日：2005-03-08

申请号：US09915668

申请日：2001-07-26

申请人： Jody Bern Joyner ,  Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung

发明人： Jody Bern Joyner ,  Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/2007

摘要： A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recovery bus. When problems arise with node operations on the high speed bus, operations are transferred to the low frequency recovery bus and continue there at a slower rate for recovery operations. The recovery technique may be used to increase system speed and performance on a dynamic basis.

摘要翻译： 多个处理节点的计算机系统以具有高速，高性能宽带宽特性的公共总线的环路配置或关闭操作。 系统中的处理节点也通过单独的窄带宽，低频恢复总线互连。 当高速总线上的节点操作出现问题时，操作将传输到低频恢复总线，并以较慢的速率继续进行恢复操作。 恢复技术可以用于在动态基础上提高系统速度和性能。

公开(公告)号：US07308558B2

公开(公告)日：2007-12-11

申请号：US10752959

申请日：2004-01-07

申请人： Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

发明人： Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

IPC分类号： G06F15/16 ,  G06F16/163

CPC分类号： G06F15/17381

摘要： The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.

摘要翻译： 数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。 在一个应用中，数据处理系统包括第一和第二处理簿，每个书籍至少包括第一和第二处理单元。 第一和第二处理单元中的每一个具有相应的第一输出数据总线。 第一处理单元的第一输出数据总线耦合到第二处理单元，第二处理单元的第一输出数据总线耦合到第一处理单元。 至少第一处理簿的第一处理单元和第二处理簿的第二处理单元各自具有相应的第二输出数据总线。 第一处理簿的第一处理单元的第二输出数据总线耦合到第二处理器书的第一处理单元，第二处理器书的第二处理单元的第二输出数据总线耦合到第二处理器 第一个处理器书的单位。

公开(公告)号：US07526631B2

公开(公告)日：2009-04-28

申请号：US10425421

申请日：2003-04-28

申请人： Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F15/8007

摘要： A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

摘要翻译： 基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。 处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。 处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。 提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片 最远的地方，反之亦然。 一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。

公开(公告)号：US20080209163A1

公开(公告)日：2008-08-28

申请号：US12118199

申请日：2008-05-09

申请人： Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F15/76

CPC分类号： G06F15/8007

摘要： A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

摘要翻译： 基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。 处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。 处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。 提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片 最远的地方，反之亦然。 一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。

公开(公告)号：US07007128B2

公开(公告)日：2006-02-28

申请号：US10752835

申请日：2004-01-07

申请人： Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

发明人： Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

IPC分类号： G06F13/00

CPC分类号： G06F13/4027

摘要： A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units. The first processing unit requests approval from the third processing unit via the control channel to transmit a data communication to the second processing unit, and the third processing unit approves or delays transmission of the data communication in a response transmitted via the control channel.

摘要翻译： 数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。 在一个实现中，数据处理系统至少包括第一到第三处理单元，耦合到多个处理单元的数据存储器和互连结构。 所述互连结构至少包括将所述第一处理单元耦合到所述第二处理单元的第一数据总线和将所述第三处理单元耦合到所述第二处理单元的第二数据总线，使得所述第一处理单元和所述第三处理单元可以向第二处理单元 处理单元。 数据处理系统还包括耦合第一和第三处理单元的控制通道。 第一处理单元经由控制信道从第三处理单元请求批准，以将数据通信发送到第二处理单元，并且第三处理单元在经由控制信道发送的响应中批准或延迟数据通信的传输。

公开(公告)号：US06519649B1

公开(公告)日：2003-02-11

申请号：US09436899

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F1516

CPC分类号： G06F12/0813

摘要： A data processing system includes an interconnect and first and second nodes, coupled to the interconnect, that each include at least one agent. Each agent within the first and second nodes outputs a snoop response in response to snooping a transaction on the interconnect. Utilizing the snoop response of each agent within the first node, first response logic within the first node produces a first cumulative combined response. This first cumulative combined response is then combined by second response logic in the second node with the snoop response of each agent in the second node to produce a second cumulative combined response. After a complete combined response is obtained in this manner, the complete combined response is distributed to all nodes so that each agent can determine its response, if any, to the transaction.

摘要翻译： 数据处理系统包括互连以及耦合到互连的第一和第二节点，每个包括至少一个代理。 第一和第二节点内的每个代理响应于窥探互连上的事务而输出一个窥探响应。 利用第一节点内的每个代理的窥探响应，第一节点内的第一响应逻辑产生第一累积组合响应。 然后，该第一累积组合响应由第二节点中的第二响应逻辑与第二节点中每个代理的窥探响应组合以产生第二累积组合响应。 在以这种方式获得完整的组合响应之后，完整的组合响应被分配给所有节点，使得每个代理可以确定其对事务的响应（如果有的话）。

公开(公告)号：US06848003B1

公开(公告)日：2005-01-25

申请号：US09436901

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F15/16 ,  G06F15/173

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each node contains a segment of the segmented data channel and each segment is coupled to at least one other segment by destination logic. In response to snooping a write request of a master agent on the interconnect, a target agent that will service the write request places its node identifier in a snoop response. When the master agent receives the combined response, which contains the node identifier of the target agent, the master agent issues on the segmented data channel a write data transaction specifying the node identifier of the target agent as a destination identifier. In response to receipt of the write data transaction, the destination logic transmits the write data transaction to a next segment only if the destination identifier does not match a node identifier associated with a node containing a current segment.

摘要翻译： 数据处理系统包括多个节点，每个节点包含至少一个代理，并且每个节点都具有相关联的节点标识符，以及分布在多个节点之间的存储器。 数据处理系统还包括一个包含分段数据信道的互连，其中每个节点包含分段数据信道的一个段，并且每个段通过目的地逻辑耦合到至少一个其它段。 响应于在互连上窥探主代理的写请求，将服务于写请求的目标代理将其节点标识符置于窥探响应中。 当主代理接收到包含目标代理的节点标识符的组合响应时，主代理在分段数据信道上发出指定目标代理的节点标识符的写数据事务作为目的地标识符。 响应于写入数据事务的接收，目的地逻辑仅在目的地标识符与与包含当前段的节点相关联的节点标识符不匹配时才将写入数据事务发送到下一个段。

公开(公告)号：US06591307B1

公开(公告)日：2003-07-08

申请号：US09436897

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F112

CPC分类号： G06F12/0815 ,  G06F12/0813 ,  G06F12/0831

摘要： A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addition, the queue, which has an associated agent, allocates an entry to service the transaction. The response logic within each node accumulates a partial combined response of its node and any preceding node until a complete combined response for all of the plurality of nodes is obtained. However, prior to the associated agent receiving the complete combined response, the queue speculatively deallocates the entry if the partial combined response indicates that an agent other than the associated agent will service the transaction.

摘要翻译： 数据处理系统包括互连，耦合到互连的多个节点，每个节点包括至少一个代理，每个节点内的响应逻辑和队列。 响应在互连上窥探事务，每个代理输出一个侦听响应。 此外，具有关联代理的队列分配一个条目来为事务提供服务。 每个节点内的响应逻辑累积其节点和任何先前节点的部分组合响应，直到获得所有多个节点的完整组合响应。 然而，在相关联的代理接收到完整的组合响应之前，如果部分组合响应指示除了相关联的代理之外的代理将服务于该事务，则队列推测性地释放该条目。

公开(公告)号：US06910062B2

公开(公告)日：2005-06-21

申请号：US09918812

申请日：2001-07-31

申请人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： H04L12/42 ,  G06F15/17 ,  G06F15/16

CPC分类号： G06F15/17

摘要： The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.

摘要翻译： 对称多处理器系统包括多个处理节点，每个节点具有多个代理，通过互连彼此连接。 请求事务由主节点中的主代理发起到所有接收节点。 生成用于与请求事务相关联的写计数器号。 主代理然后等待来自接收节点的组合响应。 在接收到组合响应之后，根据组合的响应，将数据分组从主代理发送到所有预期的接收节点。 在发送数据分组之后，主节点中的主代理准备好发送另一请求事务以及新的写计数器号，而不需要等待来自接收节点的确认。

公开(公告)号：US06671712B1

公开(公告)日：2003-12-30

申请号：US09436898

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC分类号： G06F1516

CPC分类号： G06F13/4217

摘要： A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency. The non-hierarchical interconnect architecture also permits design flexibility in that the segment of the interconnect within each node can be independently implemented by a set of buses or as a switch, depending upon cost and performance considerations.

摘要翻译： 数据处理系统包括多个节点，每个节点包含至少一个代理，以及节点内的代理可访问的数据存储。 多个节点通过包括多个非阻塞单向地址信道和至少一个单向数据信道的非分层互连来耦合。 在所有多个地址信道上分别耦合到并且窥探事务的代理只能在相关联的地址信道上发布事务。 当前的非分层互连架构采用的单向信道允许高频抽运操作对于传统的双向共享系统总线是不可能的。 另外，与传统分层系统相比，由于没有层间（例如，总线采集）通信延迟，与本地高速缓存未命中所产生的远程（高速缓存或主）存储器的访问延迟大大降低。 非分层互连架构还允许设计灵活性，因为根据成本和性能考虑，每个节点内的互连部分可以由一组总线或开关单独地实现。