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公开(公告)号：US06865695B2
公开(公告)日：2005-03-08
申请号：US09915668
申请日：2001-07-26
CPC分类号： G06F11/2007
摘要： A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recovery bus. When problems arise with node operations on the high speed bus, operations are transferred to the low frequency recovery bus and continue there at a slower rate for recovery operations. The recovery technique may be used to increase system speed and performance on a dynamic basis.
摘要翻译： 多个处理节点的计算机系统以具有高速，高性能宽带宽特性的公共总线的环路配置或关闭操作。 系统中的处理节点也通过单独的窄带宽，低频恢复总线互连。 当高速总线上的节点操作出现问题时，操作将传输到低频恢复总线，并以较慢的速率继续进行恢复操作。 恢复技术可以用于在动态基础上提高系统速度和性能。
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2.发明授权Multiprocessor data processing system having scalable data interconnect and data routing mechanism 失效具有可扩展数据互连和数据路由机制的多处理器数据处理系统公开(公告)号：US07308558B2
公开(公告)日：2007-12-11
申请号：US10752959
申请日：2004-01-07
IPC分类号： G06F15/16 , G06F16/163
CPC分类号： G06F15/17381
摘要： The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.
摘要翻译： 数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。 在一个应用中，数据处理系统包括第一和第二处理簿，每个书籍至少包括第一和第二处理单元。 第一和第二处理单元中的每一个具有相应的第一输出数据总线。 第一处理单元的第一输出数据总线耦合到第二处理单元，第二处理单元的第一输出数据总线耦合到第一处理单元。 至少第一处理簿的第一处理单元和第二处理簿的第二处理单元各自具有相应的第二输出数据总线。 第一处理簿的第一处理单元的第二输出数据总线耦合到第二处理器书的第一处理单元，第二处理器书的第二处理单元的第二输出数据总线耦合到第二处理器 第一个处理器书的单位。
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3.发明授权Data processing system with backplane and processor books configurable to support both technical and commercial workloads 失效具有背板和处理器书籍的数据处理系统可配置为支持技术和商业工作负载公开(公告)号：US07526631B2
公开(公告)日：2009-04-28
申请号：US10425421
申请日：2003-04-28
CPC分类号： G06F15/8007
摘要： A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.
摘要翻译： 基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。 处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。 处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。 提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片 最远的地方，反之亦然。 一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。
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4.发明申请DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS 审中-公开具有背板和处理器书的数据处理系统可配置以支持两种技术和商业工作公开(公告)号：US20080209163A1
公开(公告)日：2008-08-28
申请号：US12118199
申请日：2008-05-09
IPC分类号： G06F15/76
CPC分类号： G06F15/8007
摘要： A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.
摘要翻译： 基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。 处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。 处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。 提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片 最远的地方，反之亦然。 一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。
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5.发明授权Multiprocessor data processing system having a data routing mechanism regulated through control communication 失效具有通过控制通信调节的数据路由机制的多处理器数据处理系统公开(公告)号：US07007128B2
公开(公告)日：2006-02-28
申请号：US10752835
申请日：2004-01-07
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units. The first processing unit requests approval from the third processing unit via the control channel to transmit a data communication to the second processing unit, and the third processing unit approves or delays transmission of the data communication in a response transmitted via the control channel.
摘要翻译： 数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。 在一个实现中，数据处理系统至少包括第一到第三处理单元，耦合到多个处理单元的数据存储器和互连结构。 所述互连结构至少包括将所述第一处理单元耦合到所述第二处理单元的第一数据总线和将所述第三处理单元耦合到所述第二处理单元的第二数据总线，使得所述第一处理单元和所述第三处理单元可以向第二处理单元 处理单元。 数据处理系统还包括耦合第一和第三处理单元的控制通道。 第一处理单元经由控制信道从第三处理单元请求批准，以将数据通信发送到第二处理单元，并且第三处理单元在经由控制信道发送的响应中批准或延迟数据通信的传输。
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公开(公告)号：US06874063B1
公开(公告)日：2005-03-29
申请号：US09436421
申请日：1999-11-09
CPC分类号： G06F12/0831
摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.
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7.发明授权公开(公告)号：US06349360B1
公开(公告)日：2002-02-19
申请号：US09436419
申请日：1999-11-09
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/30185 , G06F9/383 , G06F12/0877
摘要： A method for preferentially ordering the retrieval of data from a system component, such as a cache line of a cache. The method includes the steps of first encoding a set of bits with a processor-preferred order of data retrieval. In the cache embodiment, the set of bits is then sent along with the read request via the address bus to the cache. A modified cache controller having preference order logic or a preference order logic component interprets the set of bits and directs the retrieval of the requested data from the cache line according to the preferred order. In one embodiment, a hierarchial preference order is utilized. The preference order logic attempts to retrieve the data according to the highest preference order. If that preference order cannot be utilized, due to other considerations, the next highest preference order is attempted.
摘要翻译： 用于优先排序从诸如高速缓存的高速缓存行的系统组件检索数据的方法。 该方法包括以处理器优选的数据检索顺序对一组位进行编码的步骤。 在缓存实施例中，然后将该组位与经由地址总线的读取请求一起发送到高速缓存。 具有偏好顺序逻辑或偏好顺序逻辑组件的经修改的高速缓存控制器根据优选顺序来解释该组位并且指示从高速缓存行检索所请求的数据。 在一个实施例中，利用层级偏好顺序。 优先顺序逻辑尝试根据最高优先级顺序检索数据。 如果该偏好顺序不能被利用，由于其他考虑，尝试下一个最高优先顺序。
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公开(公告)号：US07308536B2
公开(公告)日：2007-12-11
申请号：US11041711
申请日：2005-01-22
CPC分类号： G06F12/0831
摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.
摘要翻译： 一种用于向处理器通知所选择的数据传输顺序的处理器的方法。 该方法包括以下步骤：将系统组件经由数据总线耦合到处理器以实现数据传输，在系统组件逻辑处确定将数据发送到处理器的顺序，以及向数据总线发出与 数据，其中所选择的订单位向处理器提醒订单，并且以该顺序传送数据。 在优选实施例中，系统组件是高速缓存，并且该方法可以涉及在高速缓存处接收对来自处理器的读取地址/请求的排序的偏好。 高速缓存控制器或偏好顺序逻辑组件的偏好顺序逻辑通过将处理器偏好与其他偏好（包括高速缓存顺序偏好）进行比较来评估期望的顺序的偏好。 选择一个偏好顺序，然后以所选顺序从高速缓存的高速缓存行检索数据。
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9.发明授权公开(公告)号：US06535957B1
公开(公告)日：2003-03-18
申请号：US09436422
申请日：1999-11-09
IPC分类号： G06F932
CPC分类号： G06F9/30043 , G06F9/30185 , G06F9/34 , G06F12/0879
摘要： A method for selecting an order of data transmittal based on system bus utilization of a data processing system. The method comprises the steps of coupling system components to a processor within the data processing system to effectuate data transfer, dynamically determining based on current system bus loading, an order in which to retrieve and transmit data from the system component to the processor, and informing the processor of the order selected by issuing to the data bus a plurality of selected order bits concurrent with the transmittal of the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is a cache and a system monitor monitors the system bus usage/loading. When a read request appears at the cache, the modified cache controller preference order logic or a preference order logic component determines the order to transmit the data wherein the order is selected to substantially optimize data bandwidth when the system bus usage is high and selected to substantially optimize data latency when system bus usage is low.
摘要翻译： 一种基于数据处理系统的系统总线利用率来选择数据传输顺序的方法。 该方法包括以下步骤：将系统组件耦合到数据处理系统内的处理器以实现数据传输，基于当前系统总线负载动态确定，从系统组件检索和传输数据到处理器的顺序，以及通知 所述处理器通过向所述数据总线发送与所述数据的传送同时发送的多个所选顺序位而选择的所述顺序，其中所述选择的顺序位向所述处理器报告所述顺序并且所述数据以该顺序被传送。 在优选实施例中，系统组件是高速缓存，系统监视器监视系统总线的使用/加载。 当读取请求出现在高速缓存时，修改的高速缓存控制器偏好顺序逻辑或偏好顺序逻辑组件确定发送数据的顺序，其中当系统总线使用率高时选择该顺序以基本上优化数据带宽并且被选择为基本上 当系统总线使用率低时优化数据延迟。
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10.发明授权System bus read address operations with data ordering preference hint bits for vertical caches 失效系统总线读地址操作与垂直高速缓存的数据排序偏好提示位公开(公告)号：US06360297B1
公开(公告)日：2002-03-19
申请号：US09436420
申请日：1999-11-09
IPC分类号： G06F1208
CPC分类号： G06F12/0879 , G06F12/0897
摘要： A method for preferentially ordering the retrieval of data from a cache line of a cache within a vertical cache configuration. The method includes the steps of first encoding a set of bits with a processor-preferred order of data retrieval based on the cache configuration. The set of bits is then sent along with the read request via the address bus to the first cache. The cache directory is check to see if a “hit” occurs (i.e., the data is present in that cache). If the data is present, a modified cache controller having preference order logic or a preference order logic component interprets the set of bits and directs the retrieval of the requested data from the cache line according to the preferred order for that cache. If no hit (i.e., a miss) occurs, the read request and the preferred order set of bits are sent to the next level cache. In one embodiment, a single set of bits is utilized. The preference order logic encodes the set of bits with the preference order of the next level cache when a miss occurs, prior to sending the read request and the set of bits to the next level cache. When all levels of cache result in a miss, the read request is sent over the system bus with the preference order set of bits being encoded for the system wide preference.
摘要翻译： 一种用于优先排序从垂直高速缓存配置中的高速缓存行的高速缓存行检索数据的方法。 该方法包括以下步骤：基于高速缓存配置，以处理器优选的数据检索顺序对一组位进行编码。 然后将该组位与经由地址总线的读取请求一起发送到第一高速缓存。 检查缓存目录以查看是否发生“命中”（即数据存在于该高速缓存中）。 如果存在数据，则具有偏好顺序逻辑或偏好顺序逻辑组件的修改的高速缓存控制器根据该高速缓存的优选次序来解释该组位并且指示从高速缓存行检索所请求的数据。 如果没有发生命中（即，未命中），则读取请求和优选的比特顺序集合被发送到下一级高速缓存。 在一个实施例中，使用单组位。 在将读请求和该组位发送到下一级高速缓存之前，首选顺序逻辑将在发生未命中时以下一级高速缓存的优先顺序对该组进行编码。 当所有级别的缓存导致错过时，读取请求通过系统总线发送，优先级顺序集合被编码为系统广泛偏好。
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