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    Method and arrangement providing for implementation granularity using implementation sets
    1.
    发明授权
    Method and arrangement providing for implementation granularity using implementation sets 有权
    使用实现集提供实现粒度的方法和布置

    公开(公告)号：US08296690B1

    公开(公告)日：2012-10-23

    申请号：US12027501

    申请日：2008-02-07

    申请人： Raymond Kong ,  Daniel J. Downs ,  John J. Laurence ,  Richard Yachyang Sun ,  Sankaranarayanan Srinivasen

    发明人： Raymond Kong ,  Daniel J. Downs ,  John J. Laurence ,  Richard Yachyang Sun ,  Sankaranarayanan Srinivasen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

    摘要翻译： 基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级 通过每个节点。 每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

    Method and system for managing behavior of algorithms
    3.
    发明授权
    Method and system for managing behavior of algorithms 有权
    用于管理算法行为的方法和系统

    公开(公告)号：US07290241B1

    公开(公告)日：2007-10-30

    申请号：US10913752

    申请日：2004-08-06

    申请人： Daniel J. Downs ,  John D. Bunte ,  Raymond Kong ,  John J. Laurence ,  Richard Yachyang Sun

    发明人： Daniel J. Downs ,  John D. Bunte ,  Raymond Kong ,  John J. Laurence ,  Richard Yachyang Sun

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

    摘要翻译： 一种管理算法行为的方法包括指定管理I-Set实现指令，命令行选项和环境变量的管理规则/策略，并将管理规则/策略加载到行为管理器中。 在客户端工具中，I-Set层次结构一次处理并迭代一个I-Set节点。 没有更多的I-Sets要处理，该方法就完成了。 如果更多，那么该工具将使用具有查询行为的符号指示符的I-Set查询“行为管理器”。 行为管理器可以回复客户端工具，指示是否在I-Set节点的相应逻辑上支持查询行为。 如果I-Set节点的算法缺少查询行为，则另一个I-Set可能需要处理。 如果I-Set节点的算法具有查询行为，则客户端工具将相应的算法应用于适当的逻辑。

    Method and system for implementing a circuit design in a tree representation
    4.
    发明授权
    Method and system for implementing a circuit design in a tree representation 有权
    在树形表示中实现电路设计的方法和系统

    公开(公告)号：US07146583B1

    公开(公告)日：2006-12-05

    申请号：US10912999

    申请日：2004-08-06

    申请人： Richard Yachyang Sun ,  Daniel J. Downs ,  Raymond Kong ,  John J. Laurence

    发明人： Richard Yachyang Sun ,  Daniel J. Downs ,  Raymond Kong ,  John J. Laurence

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5072

    摘要： A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.

    摘要翻译： 在树形表示中实现用户集成电路（IC）设计的方法包括以包括至少一个子设计的分区方式引入用户IC设计的树表示以形成用户设计的设计抽象的步骤。 至少一个子设计可以包括提供多级实现层次的子设计。 该方法还可以包括以自顶向下的方式遍历设计抽象以提供从至少一个子设计的楼层规划，端口分配和时间预算中选择的功能的步骤，以及遍历设计抽象的步骤 自下而上的方式，以促进资源冲突的解决和多个子设计的并行处理中的至少一个。 以自下而上的方式遍历设计抽象可以有助于对集成电路设计的时序进行重新预算。

    Method and arrangement providing for implementation granularity using implementation sets
    5.
    发明授权
    Method and arrangement providing for implementation granularity using implementation sets 有权
    使用实现集提供实现粒度的方法和布置

    公开(公告)号：US07360177B1

    公开(公告)日：2008-04-15

    申请号：US10913000

    申请日：2004-08-06

    申请人： Raymond Kong ,  Daniel J. Downs ,  John J. Laurence ,  Richard Yachyang Sun ,  Sankaranarayanan Srinivasan

    发明人： Raymond Kong ,  Daniel J. Downs ,  John J. Laurence ,  Richard Yachyang Sun ,  Sankaranarayanan Srinivasan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

    摘要翻译： 基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级 通过每个节点。 每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

    Method and system for designing integrated circuits using implementation directives
    6.
    发明授权
    Method and system for designing integrated circuits using implementation directives 有权
    使用实施指令设计集成电路的方法和系统

    公开(公告)号：US07181704B1

    公开(公告)日：2007-02-20

    申请号：US10913746

    申请日：2004-08-06

    申请人： Daniel J. Downs ,  Raymond Kong ,  John J. Laurence ,  Sankaranarayanan Srinivasan ,  Richard Yachyang Sun

    发明人： Daniel J. Downs ,  Raymond Kong ,  John J. Laurence ,  Sankaranarayanan Srinivasan ,  Richard Yachyang Sun

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

    摘要翻译： 使用用于流量控制的实施指令来设计集成电路的方法可以包括加载设计以及指定约束的步骤，创建由部分网表形成的数据结构的至少一个实例，并且分解至少一组高级别 规则到简单的实施指令。 该方法还可以包括以下步骤：将简单实施指令有选择地附加到数据结构，实现查询数据结构节点以创建要在数据结构上执行的任务列表的任务管理器，以及使用 通用流引擎。

    Implementation set-based guide engine and method of implementing a circuit design
    7.
    发明授权
    Implementation set-based guide engine and method of implementing a circuit design 有权
    实现集导向引擎和实现电路设计的方法

    公开(公告)号：US07171644B1

    公开(公告)日：2007-01-30

    申请号：US10912957

    申请日：2004-08-06

    申请人： John J. Laurence ,  Daniel J. Downs ,  Raymond Kong ,  Richard Yachyang Sun

    发明人： John J. Laurence ,  Daniel J. Downs ,  Raymond Kong ,  Richard Yachyang Sun

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.

    摘要翻译： 实现集成电路设计的方法可以包括形成基本实现集合并形成具有多个指导实施集节点的指导实现集的步骤。 该方法还可以包括以下步骤：在多个指导实施集节点中的至少一个引导实施集节点（或每个节点）上存储指令。 该方法还可以包括以下步骤：在多个指导实施集节点中的至少一个指导实施集节点（或每个节点）上创建和存储任务。 该方法还可以包括在引导实现集树中的每个节点被访问时调用在指导实现集合节点上存储的每个任务的步骤。

    Run-time efficient methods for routing large multi-fanout nets
    8.
    发明授权
    Run-time efficient methods for routing large multi-fanout nets 有权
    运行时高效的路由大型多扇出网络的方法

    公开(公告)号：US08015535B1

    公开(公告)日：2011-09-06

    申请号：US12050447

    申请日：2008-03-18

    申请人： Raymond Kong ,  Anirban Rahut

    发明人： Raymond Kong ,  Anirban Rahut

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

    摘要翻译： 限制可用于路由多扇出网络的集成电路（IC）的路由资源的方法可以包括选择包括源和多个负载的多扇出网络，并且识别IC的每个区域 不包括多个负载中的至少一个。 每个区域可以具有限定的几何形状。 可以选择一种类型的路由资源，其具有相对于IC的物理取向，其对应于IC的区域的几何形状。 当路由多扇出网时，可以排除位于IC区域内不包括多个负载中的至少一个的所选类型的每个路由资源。

    Placing partitioned circuit designs within iterative implementation flows
    9.
    发明授权
    Placing partitioned circuit designs within iterative implementation flows 有权
    将分隔电路设计放在迭代实现流程中

    公开(公告)号：US07590960B1

    公开(公告)日：2009-09-15

    申请号：US11787925

    申请日：2007-04-18

    申请人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

    发明人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5072

    摘要： A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

    摘要翻译： 将分割电路设计的电路元件放置在目标可编程逻辑器件（PLD）上的方法可以包括将电路设计的电路元件映射到电路设计的相应分区，选择电路设计的电路元件，以及选择候选 位于目标PLD的逻辑边界内。 该方法还可以包括至少部分地根据所选择的电路元件是否属于与已经放置在逻辑边界内的至少一个其它电路元件的电路设计的相同分区来验证所选择的电路元件的候选位置。 所选择的电路元件可以根据验证选择性地放置在候选位置。