公开(公告)号：US20200350922A1

公开(公告)日：2020-11-05

申请号：US16853970

申请日：2020-04-21

申请人： Realtek Semiconductor Corporation

发明人： Xiao-Bo ZHOU ,  Shih-Hsiung HUANG

IPC分类号： H03M1/46 ,  H03M1/36

摘要： An analog to digital converting module includes a comparator, at least one digital to analog convertor, and a reference buffer. The comparator is configured to compare a first input signal and a second input signal so as to output a comparing signal. The at least one at least one digital to analog convertor includes at least one capacitor. The reference buffer is configured to provide a reference signal. The at least one digital to analog convertor receives the reference signal such that a ripple signal is generated according to a change of a voltage of the reference signal. The capacitance of the capacitor of the at least one digital to analog convertor is adjusted based on the ripple signal.

公开(公告)号：US20200274544A1

公开(公告)日：2020-08-27

申请号：US16785763

申请日：2020-02-10

申请人： Realtek Semiconductor Corporation

发明人： Xiao-Bo ZHOU

IPC分类号： H03M1/10

摘要： A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.

公开(公告)号：US20180159550A1

公开(公告)日：2018-06-07

申请号：US15693450

申请日：2017-08-31

申请人： Realtek Semiconductor Corporation

发明人： Xiao-Bo ZHOU

IPC分类号： H03M3/00

CPC分类号： H03M3/37 ,  H03M1/742 ,  H03M3/454 ,  H03M3/464 ,  H03M3/494

摘要： A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.