Power-save system for detection of Bluetooth long range packets

    公开(公告)号:US10425895B2

    公开(公告)日:2019-09-24

    申请号:US16221561

    申请日:2018-12-16

    Abstract: A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc−2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.

    Ultra Low Power Mesh Network
    5.
    发明申请

    公开(公告)号:US20190149343A1

    公开(公告)日:2019-05-16

    申请号:US15811690

    申请日:2017-11-14

    Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

    Quick decision preamble detector with hierarchical processing

    公开(公告)号:US10292104B2

    公开(公告)日:2019-05-14

    申请号:US15682541

    申请日:2017-08-21

    Abstract: A wireless receiver has a preamble detection apparatus and method which waits until the expected arrival of a beacon frame, after which power is cyclically applied during a preamble detection interval and a sleep interval until a preamble is detected. The preamble detector has a first mode with a longer preamble detection interval and a second mode with a shorter preamble detection interval. During the preamble detection interval, power is applied to receiver components, and during the sleep interval, power is not applied. The duration of the preamble detection interval is equal to a preamble sensing interval, and if a preamble is detected, power remains applied to a preamble processor for a preamble processing interval. The duration of the sleep interval is the duration of a long preamble less the sum of two times the preamble detection interval plus the preamble processing interval. Phase lock loop (PLL) power is applied a PLL settling time prior to and during the preamble detection interval.

    Hierarchical Wakeup Apparatus and Method
    7.
    发明申请

    公开(公告)号:US20190191372A1

    公开(公告)日:2019-06-20

    申请号:US15845813

    申请日:2017-12-18

    Abstract: A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.

    Multi-threaded processor with thread granularity

    公开(公告)号:US11288072B2

    公开(公告)日:2022-03-29

    申请号:US16945936

    申请日:2020-08-03

    Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

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