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公开(公告)号：US09703899B1
公开(公告)日：2017-07-11
申请号：US14829530
申请日：2015-08-18
Applicant: Redpine Signals, Inc.
Inventor： Venkat Mattela , Narasimhan Venkatesh , Dhiraj Sogani , Apurva Peri
CPC classification number: G06F17/50 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/02 , H05K3/0005
Abstract: A product synthesizer has a core CPU, power distribution, and a plurality of selectable interfaces, each interface having an associated schematic symbol, PCB symbol, mechanical model, power dissipation, and power requirement. A set of constraints identifies performance metrics including low power, high performance, battery or mains power, battery life, and other constraints. The product synthesizer receives as inputs the interfaces and constraints, and generates as outputs a schematic diagram, a bill of materials, a routed printed circuit board, and a solid model of an enclosure, all of which satisfy the constraints and include the identified interfaces.
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公开(公告)号：US11355517B2
公开(公告)日：2022-06-07
申请号：US17006818
申请日：2020-08-29
Applicant: Redpine Signals, Inc.
Inventor： Venkat Mattela , Sanghamitra Debroy , Santhosh Sivasubramani , Amit Acharyya
Abstract: An AND or OR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a AND or OR logic function on applied input magnetization.
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公开(公告)号：US11288072B2
公开(公告)日：2022-03-29
申请号：US16945936
申请日：2020-08-03
Applicant: Redpine Signals, Inc.
Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.
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公开(公告)号：US11106268B2
公开(公告)日：2021-08-31
申请号：US16445238
申请日：2019-06-19
Applicant: Redpine Signals, Inc.
Inventor： Subba Reddy Kallam , Venkat Mattela , Aravinth Kumar Ayyappannair Radhadevi , Sesha Sairam Regulagadda
Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).
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Patent Agency Ranking
公开(公告)号：US11101800B1
公开(公告)日：2021-08-24
申请号：US17006819
申请日：2020-08-29
Applicant: Redpine Signals, Inc.
Inventor： Venkat Mattela , Sanghamitra Debroy , Santhosh Sivasubramani , Amit Acharyya
IPC: H03K19/0175
Abstract: An NAND or NOR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a NAND, or NOR logic function on applied input magnetization.
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公开(公告)号：US09697162B1
公开(公告)日：2017-07-04
申请号：US14829550
申请日：2015-08-18
Applicant: Redpine Signals, Inc.
Inventor： Venkat Mattela , Narasimhan Venkatesh , Dhiraj Sogani , Apurva Peri
CPC classification number: G06F13/4068 , G06F1/266 , G06F13/40 , G06F17/5009 , G06F17/5068 , G06F17/5072
Abstract: A product synthesizer has a core CPU, power distribution, and a plurality of selectable interfaces, each interface having an associated schematic symbol, PCB symbol, mechanical model, power dissipation, and power requirement. A set of constraints identifies performance metrics including low power, high performance, battery or mains power, battery life, and other constraints. The product synthesizer receives as inputs the interfaces and constraints, and generates as outputs a schematic diagram, a bill of materials, a routed printed circuit board, and a solid model of an enclosure, all of which satisfy the constraints and include the identified interfaces.
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公开(公告)号：US11689443B2
公开(公告)日：2023-06-27
申请号：US17334703
申请日：2021-05-29
Applicant: Redpine Signals, Inc.
Inventor： Robert Wiser , Venkat Mattela , Wei Xiong
IPC: H04L45/02
CPC classification number: H04L45/08
Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.
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公开(公告)号：US11641783B2
公开(公告)日：2023-05-02
申请号：US17114498
申请日：2020-12-08
Applicant: Redpine Signals, Inc.
Inventor： Venkat Mattela , Sanghamitra Debroy , Santhosh Sivasubramani , Amit Acharyya
Abstract: An adder device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A set of regions are positioned on a top layer above a continuous bottom layer, and the regions excited with magnetization for A and not A, B and not B, and C and not C to form a sum and an inverse carry output magnetization.
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公开(公告)号：US10356092B2
公开(公告)日：2019-07-16
申请号：US15684854
申请日：2017-08-23
Applicant: Redpine Signals, Inc.
Inventor： Venkat Mattela , Duen Jeng Wang
Abstract: An IoT device has a public device identifier and a private device identifier, where the public device identifier is publicly available and the private device identifier is secret but kept in a secure device database as a correspondence. A registration request is sent from the IoT device to an association server in communication with the device database having an association between IoT public identifier and a corresponding IoT private identifier. The association server which receives the registration request responds with a registration acknowledgement containing, in encrypted form, the private device identifier of the original request and, optionally, the public device identifier associated with the registration request. The requesting IoT device receives the association acknowledgement, decrypts the private device identifier, compares it to its own device identifier, and if they match, sends one or more association requests.
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