公开(公告)号：US10931301B2

公开(公告)日：2021-02-23

申请号：US16715759

申请日：2019-12-16

Applicant: Redpine Signals, Inc.

Inventor： Subba Reddy Kallam ,  Sriram Mudulodu

IPC: H03M7/00 ,  H03M7/30 ,  G06F9/30 ,  G06F9/22 ,  G06F16/901

Abstract: A code decompression engine reads compressed code from a memory containing a series of code parts and a dictionary part. The code parts each have a bit indicating compressed or uncompressed. When the code part is compressed, it has a value indicating the number of segments, followed by the segments, followed by an index into the dictionary part. The decompressed instruction is the dictionary value specified by the index, which is modified by the segments. Each segment describes the modification to the dictionary part specified by the index by a mask type, a mask offset, and a mask.

公开(公告)号：US11288072B2

公开(公告)日：2022-03-29

申请号：US16945936

申请日：2020-08-03

Applicant: Redpine Signals, Inc.

Inventor： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkat Mattela ,  Venkata Siva Prasad Pulagam

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.

公开(公告)号：US11106268B2

公开(公告)日：2021-08-31

申请号：US16445238

申请日：2019-06-19

Applicant: Redpine Signals, Inc.

Inventor： Subba Reddy Kallam ,  Venkat Mattela ,  Aravinth Kumar Ayyappannair Radhadevi ,  Sesha Sairam Regulagadda

IPC: G06F1/32 ,  G06F15/80 ,  G06F1/3234 ,  H03M1/80 ,  G06F1/06 ,  H03M1/12 ,  G06F7/544 ,  H03M1/66

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

公开(公告)号：US11307779B2

公开(公告)日：2022-04-19

申请号：US16992098

申请日：2020-08-13

Applicant: Redpine Signals, Inc.

Inventor： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkata Siva Prasad Pulagam ,  Anusha Biyyani ,  Venkatesh Vinjamuri ,  Shahabuddin Mohammed ,  Rahul Kumar Gurram ,  Akhil Soni

IPC: G06F3/06 ,  G06F12/06

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

公开(公告)号：US11032766B2

公开(公告)日：2021-06-08

申请号：US16442446

申请日：2019-06-14

Applicant: Redpine Signals, Inc.

Inventor： Partha Sarathy Murali ,  Subba Reddy Kallam

IPC: H04W52/02 ,  H04W52/24 ,  H04B17/318 ,  H04W4/80 ,  H04L9/08 ,  H04W84/20 ,  H04R1/10 ,  H04R5/033 ,  G10L19/02

Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.

公开(公告)号：US10541708B1

公开(公告)日：2020-01-21

申请号：US16140526

申请日：2018-09-24

Applicant: Redpine Signals, Inc.

Inventor： Subba Reddy Kallam ,  Sriram Mudulodu

IPC: H03M7/00 ,  H03M7/30 ,  G06F9/30 ,  G06F9/22 ,  G06F16/901

Abstract: A code decompression engine reads compressed code from a memory containing a compressed code part and a dictionary part. The compressed code part contains a series of instructions being either an uncompressed instruction preceded by an uncompressed code bit, or a compressed instruction having a compressed code bit followed by a number of segments field followed by segments, followed by a directory index indication a directory location to read. Each segment consists of a mask type, a mask offset, and a mask.