公开(公告)号：US11176979B2

公开(公告)日：2021-11-16

申请号：US16803454

申请日：2020-02-27

Applicant: Regents of the University of Minnesota

Inventor： Jian-Ping Wang ,  Sachin S. Sapatnekar ,  Ulya R. Karpuzcu ,  Zhengyang Zhao ,  Masoud Zabihi ,  Michael Salonik Resch ,  Zamshed I. Chowdhury ,  Thomas Peterson

IPC: G11C11/00 ,  G11C11/16

Abstract: A logic-memory cell includes a spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals is capable of changing a resistance between the first and second terminals. In the cell, a first transistor is connected between a logic connection line and the first terminal of the spin-orbit torque device and a second transistor is connected between the logic connection line and the third terminal of the spin-orbit torque device.

公开(公告)号：US20200279597A1

公开(公告)日：2020-09-03

申请号：US16803454

申请日：2020-02-27

Applicant: Regents of the University of Minnesota

Inventor： Jian-Ping Wang ,  Sachin S. Sapatnekar ,  Ulya R. Karpuzcu ,  Zhengyang Zhao ,  Masoud Zabihi ,  Michael Salonik Resch ,  Zamshed I. Chowdhury ,  Thomas Peterson

IPC: G11C11/16

Abstract: A logic-memory cell includes a spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals is capable of changing a resistance between the first and second terminals. In the cell, a first transistor is connected between a logic connection line and the first terminal of the spin-orbit torque device and a second transistor is connected between the logic connection line and the third terminal of the spin-orbit torque device.

公开(公告)号：US11573586B2

公开(公告)日：2023-02-07

申请号：US17410896

申请日：2021-08-24

Applicant: University of South Florida ,  REGENTS OF THE UNIVERSITY OF MINNESOTA

Inventor： Selçuk Köse ,  Longfei Wang ,  S. Karen Khatamifard ,  Ulya R. Karpuzcu

IPC: G05F1/59 ,  G05F1/614 ,  G05F1/563 ,  G05F1/56 ,  G05F1/575 ,  G05F1/565

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

公开(公告)号：US11493945B1

公开(公告)日：2022-11-08

申请号：US16692389

申请日：2019-11-22

Applicant: University of South Florida ,  REGENTS OF THE UNIVERSITY OF MINNESOTA

Inventor： Longfei Wang ,  S. Karen Khatamifard ,  Ulya R. Karpuzcu ,  Selçuk Köse

IPC: G05F1/00 ,  G05F1/59 ,  G05F1/575

Abstract: An apparatus and method are provided for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by the effects of aging on the power transistors of the DLDO, such as by the effects of negative bias temperature instability (NBTI)-induced aging, for example. The apparatus comprises a shift register for use in a DLDO that is configured to activate and deactivate power transistors of the DLDO to evenly distribute electrical stress among the transistors in a way that mitigates performance degradation of the DLDO under various load current conditions. In addition, the shift register and methodology can be implemented in such a way that nearly no extra power and area overhead are consumed.