公开(公告)号：US08095904B2

公开(公告)日：2012-01-10

申请号：US12055888

申请日：2008-03-26

申请人： Renato Fernandes Hentschke ,  Marcelo de Oliveira Johann ,  Jagannathan Narasimhan ,  Ricardo Augusto de Luz Reis

发明人： Renato Fernandes Hentschke ,  Marcelo de Oliveira Johann ,  Jagannathan Narasimhan ,  Ricardo Augusto de Luz Reis

IPC分类号： G06F17/50

CPC分类号： H04L45/00 ,  H04L45/48

摘要： A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.

摘要翻译： 提供了一种制造灵活的定时驱动路由树的方法。 两个或多个目标节点根据数据临界性进行排序。 源 - 汇网格是从一个或多个源节点和两个或多个目标节点构建的。 构建包括一个或多个源节点的初始路由树。 在初始路由树上执行路由树生成算法，根据用户定义的定时因子利用排序的两个或多个目标节点和源 - 宿网格构建灵活的定时驱动路由树。 用户定义的时序因子规定了从一个或多个源节点中的给定的一个到多个目标节点中的给定的一个的路由路径的隔离程度。

公开(公告)号：US07571411B2

公开(公告)日：2009-08-04

申请号：US11330937

申请日：2006-01-12

申请人： Renato Fernandes Hentschke ,  Marcelo de Oliveira Johann ,  Jagannathan Narasimhan ,  Ricardo Augusto de Luz Reis

发明人： Renato Fernandes Hentschke ,  Marcelo de Oliveira Johann ,  Jagannathan Narasimhan ,  Ricardo Augusto de Luz Reis

IPC分类号： G06F17/50

CPC分类号： H04L45/00 ,  H04L45/48

摘要： A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.

摘要翻译： 提供了一种制造灵活的定时驱动路由树的方法。 两个或多个目标节点根据数据临界性进行排序。 源 - 汇网格是从一个或多个源节点和两个或多个目标节点构建的。 构建包括一个或多个源节点的初始路由树。 在初始路由树上执行路由树生成算法，根据用户定义的定时因子利用排序的两个或多个目标节点和源 - 宿网格构建灵活的定时驱动路由树。 用户定义的时序因子规定了从一个或多个源节点中的给定的一个到多个目标节点中的给定的一个的路由路径的隔离程度。

公开(公告)号：US20080170514A1

公开(公告)日：2008-07-17

申请号：US12055888

申请日：2008-03-26

申请人： Renato Fernandes Hentschke ,  Marcelo De Oliveira Johann ,  Jagannathan Narasimhan ,  Ricardo Augusto De Luz Reis

发明人： Renato Fernandes Hentschke ,  Marcelo De Oliveira Johann ,  Jagannathan Narasimhan ,  Ricardo Augusto De Luz Reis

IPC分类号： H04L12/28

CPC分类号： H04L45/00 ,  H04L45/48

摘要： A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.

摘要翻译： 提供了一种制造灵活的定时驱动路由树的方法。 两个或多个目标节点根据数据临界性进行排序。 源 - 汇网格是从一个或多个源节点和两个或多个目标节点构建的。 构建包括一个或多个源节点的初始路由树。 在初始路由树上执行路由树生成算法，根据用户定义的定时因子利用排序的两个或多个目标节点和源 - 宿网格构建灵活的定时驱动路由树。 用户定义的时序因子规定了从一个或多个源节点中的给定一个到两个或更多个目标节点中的给定一个的路由路径的隔离程度。

公开(公告)号：US07469395B2

公开(公告)日：2008-12-23

申请号：US11952544

申请日：2007-12-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。 第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度 线。

公开(公告)号：US20080074147A1

公开(公告)日：2008-03-27

申请号：US11952544

申请日：2007-12-07

申请人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

发明人： John Cohn ,  Alvar Dean ,  Amir Farrahi ,  David Hathaway ,  Thomas Lepsic ,  Jagannathan Narasimhan ,  Scott Tetreault ,  Sebastian Ventrone

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有不小于预先选择的最小相同方向切换概率phi，SD，MIN或/或具有相同方向的切换概率，每时钟周期 每个时钟周期的相反方向切换概率Φ不小于预先选择的最小相对方向切换概率φi，MIN 。 第一线和第二线满足至少一个数学关系，其涉及公平和平坦，其中，W SPACING 被定义为 第一线和第二线，以及公共被定义为第一线和第二线的公共行程长度。

公开(公告)号：US06611945B1

公开(公告)日：2003-08-26

申请号：US09696718

申请日：2000-10-25

申请人： Jagannathan Narasimhan ,  Amir Farrahi

发明人： Jagannathan Narasimhan ,  Amir Farrahi

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F2217/10 ,  G06F2217/78

摘要： A method is provided for computing signal and switching probabilities at an output of a logic circuit in a network having multiple logic circuits. The method for computing the signal and switching probabilities includes steps of creating a truth table for a logic circuit where the truth table has entries respectively corresponding to signals at inputs of the logic circuit, choosing in sequence one of entries each representing switching of a signal at the output of the circuit, determining whether a signal at an input corresponding to the chosen entry is at logic high, assigning an event probability representing that the signal is at logic high, and accumulating event probabilities respectively assigned to signals at inputs corresponding to the chosen entries to produce the signal probability at the output of the circuit.

摘要翻译： 提供一种用于在具有多个逻辑电路的网络中的逻辑电路的输出处计算信号和切换概率的方法。 用于计算信号和切换概率的方法包括以下步骤：为逻辑电路创建真值表，其中真值表具有分别对应于逻辑电路的输入处的信号的条目，顺序地选择一个表示在 电路的输出，确定与所选择的条目相对应的输入处的信号是否处于逻辑高电平，分配表示该信号处于逻辑高电平的事件概率，以及分别分配给与所选择的输入相对应的输入端的信号的事件概率 条目在电路的输出端产生信号概率。

公开(公告)号：US08392866B2

公开(公告)日：2013-03-05

申请号：US12972934

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。 可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

公开(公告)号：US08271920B2

公开(公告)日：2012-09-18

申请号：US12868086

申请日：2010-08-25

申请人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

摘要翻译： 示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成， 对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

公开(公告)号：US06985004B2

公开(公告)日：2006-01-10

申请号：US09781369

申请日：2001-02-12

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： H03K17/16

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

公开(公告)号：US20120159418A1

公开(公告)日：2012-06-21

申请号：US12972934

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。 可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。