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公开(公告)号：US10115772B2
公开(公告)日：2018-10-30
申请号：US15334846
申请日：2016-10-26
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Makoto Ueki , Koji Masuzaki , Takashi Hase , Yoshihiro Hayashi
Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.
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公开(公告)号：US09711216B2
公开(公告)日：2017-07-18
申请号：US14962777
申请日：2015-12-08
Applicant: Renesas Electronics Corporation
Inventor： Takashi Hase , Naoya Furutake , Koji Masuzaki
CPC classification number: G11C13/0069 , G11C13/0064 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/72 , G11C2213/79 , G11C2213/82
Abstract: When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.
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公开(公告)号：US09679647B2
公开(公告)日：2017-06-13
申请号：US15099660
申请日：2016-04-15
Applicant: Renesas Electronics Corporation
Inventor： Makoto Ueki , Koji Masuzaki , Masaharu Matsudaira , Takashi Hase , Yoshihiro Hayashi
CPC classification number: G11C13/0069 , G11C13/004 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0092 , G11C2213/79 , G11C2213/82
Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.
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