公开(公告)号：US20150060875A1

公开(公告)日：2015-03-05

申请号：US14464912

申请日：2014-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ippei Kume ,  Hiroshi Takeda ,  Toshiharu Nagumo ,  Takashi Hase

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/7849 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66522 ,  H01L29/66659 ,  H01L29/7835

Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

Abstract translation: 实现具有高迁移率和高击穿电压的常关型晶体管。 化合物半导体层形成在基板的上方，具有p型杂质的浓度和小于1×1016 / cm3的n型杂质的浓度，并且包括III族氮化物化合物。 阱是p型杂质层，并形成在化合物半导体层中。 源极区形成在阱内并且是n型杂质层。 在化合物半导体层中形成低浓度的n型区域并与该阱连接。 在化合物半导体层中形成漏极区，并且经由低浓度n型区位于与阱相反的一侧。 漏区是n型杂质层。

公开(公告)号：US10217800B2

公开(公告)日：2019-02-26

申请号：US15697203

申请日：2017-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Ueki ,  Takashi Hase

IPC: H01L27/24 ,  H01L27/10 ,  H01L43/12 ,  H01L45/00

Abstract: A resistance change element includes first and second electrodes spaced apart from each other, a metal material layer adjacent to the first electrode, an oxide layer adjacent to each of the metal material layer and the first electrode, and a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer. The resistance change layer is made of a metal oxide. The metal material layer is made of a metal or a metal compound. The oxide layer is made of an oxide of the material forming the metal material layer. The first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper. A free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

公开(公告)号：US09711216B2

公开(公告)日：2017-07-18

申请号：US14962777

申请日：2015-12-08

Applicant: Renesas Electronics Corporation

Inventor： Takashi Hase ,  Naoya Furutake ,  Koji Masuzaki

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79 ,  G11C2213/82

Abstract: When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.

公开(公告)号：US09679647B2

公开(公告)日：2017-06-13

申请号：US15099660

申请日：2016-04-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto Ueki ,  Koji Masuzaki ,  Masaharu Matsudaira ,  Takashi Hase ,  Yoshihiro Hayashi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.

公开(公告)号：US20170290553A1

公开(公告)日：2017-10-12

申请号：US15468063

申请日：2017-03-23

Applicant: Renesas Electronics Corporation

Inventor： Masaharu Matsudaira ,  Takashi Hase ,  Akira Tanabe ,  Kazuya Uejima

IPC: A61B5/00 ,  A61B5/021 ,  A61B5/11 ,  A61B5/01

CPC classification number: A61B5/7285 ,  A61B5/0002 ,  A61B5/002 ,  A61B5/01 ,  A61B5/021 ,  A61B5/1118 ,  A61B5/742 ,  A61B2560/0209 ,  A61B2560/0242 ,  A61B2560/0252 ,  A61B2560/0431 ,  A61B2560/0475 ,  A61B2562/029

Abstract: In order to appropriately set a condition for measurement of a sensor for measuring an object to be measured in accordance with a change of an external index that can affect the object to be measured, a sensor system includes first and second sensors, a determination unit for outputting a detection signal when a measurement result of the first sensor satisfies a predetermined condition, a measurement condition storage unit for storing a condition for measurement of the second sensor, and a control unit for performing measurement by the second sensor separately from measurement in accordance with the condition for measurement, when having received the detection signal, and for updating the condition for measurement of the second sensor stored in the measurement condition storage unit based on a result of the performed measurement.

公开(公告)号：US09558824B2

公开(公告)日：2017-01-31

申请号：US14992724

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Makoto Ueki ,  Takashi Hase ,  Yoshihiro Hayashi

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: To improve information retention resistance of a resistance change memory which requires high information retention resistance. On the assumption that a special data storage memory and a general-purpose data storage memory are distinguished from each other, a forming operation small in resistance rise rate is used for an information writing operation of the special data storage memory. A switching operation is used for information writing of the general-purpose data storage memory. That is, the special data storage memory is configured so as to store information while adapting an initial resistance state to “0” whereas adapting a low resistance state to “1”. On the other hand, the general-purpose data storage memory is configured so as to store information while adapting a high resistance state to “0” whereas adapting a low resistance state to “1”.

Abstract translation: 提高需要高信息保持电阻的电阻变化存储器的信息保持电阻。 假设专用数据存储器和通用数据存储器彼此区分，电阻上升速率小的形成操作被用于特殊数据存储器的信息写入操作。 切换操作用于通用数据存储存储器的信息写入。 也就是说，特殊数据存储存储器被配置为在将初始电阻状态适配为“0”的同时存储信息，而将低电阻状态适配为“1”。 另一方面，通用数据存储存储器被配置为在使高电阻状态适应“0”的同时存储信息，而使低电阻状态适应“1”。

公开(公告)号：US09231105B2

公开(公告)日：2016-01-05

申请号：US14464912

申请日：2014-08-21

Applicant: Renesas Electronics Corporation

Inventor： Ippei Kume ,  Hiroshi Takeda ,  Toshiharu Nagumo ,  Takashi Hase

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/7849 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66522 ,  H01L29/66659 ,  H01L29/7835

Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

Abstract translation: 实现具有高迁移率和高击穿电压的常关型晶体管。 化合物半导体层形成在基板的上方，具有p型杂质的浓度和小于1×1016 / cm3的n型杂质的浓度，并且包括III族氮化物化合物。 阱是p型杂质层，并形成在化合物半导体层中。 源极区形成在阱内并且是n型杂质层。 在化合物半导体层中形成低浓度的n型区域并与该阱连接。 在化合物半导体层中形成漏极区，并且经由低浓度n型区位于与阱相反的一侧。 漏区是n型杂质层。

公开(公告)号：US10115772B2

公开(公告)日：2018-10-30

申请号：US15334846

申请日：2016-10-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Ueki ,  Koji Masuzaki ,  Takashi Hase ,  Yoshihiro Hayashi

IPC: H01L29/02 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.

公开(公告)号：US20160284405A1

公开(公告)日：2016-09-29

申请号：US14992724

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Makoto Ueki ,  Takashi Hase ,  Yoshihiro Hayashi

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: To improve information retention resistance of a resistance change memory which requires high information retention resistance. On the assumption that a special data storage memory and a general-purpose data storage memory are distinguished from each other, a forming operation small in resistance rise rate is used for an information writing operation of the special data storage memory. A switching operation is used for information writing of the general-purpose data storage memory. That is, the special data storage memory is configured so as to store information while adapting an initial resistance state to “0” whereas adapting a low resistance state to “1”. On the other hand, the general-purpose data storage memory is configured so as to store information while adapting a high resistance state to “0” whereas adapting a low resistance state to “1”.

Abstract translation: 提高需要高信息保持电阻的电阻变化存储器的信息保持电阻。 假设专用数据存储器和通用数据存储器彼此区分，电阻上升速率小的形成操作被用于特殊数据存储器的信息写入操作。 切换操作用于通用数据存储存储器的信息写入。 也就是说，特殊数据存储存储器被配置为在将初始电阻状态适配为“0”的同时存储信息，而将低电阻状态适配为“1”。 另一方面，通用数据存储存储器被配置为在使高电阻状态适应“0”的同时存储信息，而使低电阻状态适应“1”。

公开(公告)号：US20150060942A1

公开(公告)日：2015-03-05

申请号：US14455725

申请日：2014-08-08

Applicant: Renesas Electronics Corporation

Inventor： Ippei Kume ,  Takashi Onizawa ,  Takashi Hase ,  Shigeru Hirao ,  Tadatoshi Danno

IPC: H01L29/78 ,  H01L23/00 ,  H01L29/423 ,  H01L29/778 ,  H01L29/267 ,  H01L29/417

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3178 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.

Abstract translation: 有时通过作用在硅上的III族氮化物半导体的应力翘曲III族氮化物半导体和硅。 半导体器件包括衬底，缓冲层和半导体层。 沟槽形成在半导体层的第六面上。 沟槽穿过半导体层和缓冲层。 沟槽的底部至少到达衬底的内部。