公开(公告)号：US20240145586A1

公开(公告)日：2024-05-02

申请号：US18470808

申请日：2023-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/4236

Abstract: An IGBT includes first and second trenches arranged side by side on a front surface of a semiconductor substrate, a collector region formed on a back surface side of the semiconductor substrate, a body region and an emitter region provided between the first and second trenches, a first trench gate electrode provided in the first trench, a second trench gate electrode provided in the second trench, a third trench gate electrode provided below the first trench gate electrode in the first trench, a fourth trench gate electrode provided below the second trench gate electrode in the second trench, and a floating region formed in the semiconductor substrate with the first and second trenches interposed therebetween.

公开(公告)号：US20230335590A1

公开(公告)日：2023-10-19

申请号：US17720711

申请日：2022-04-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/083 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397

Abstract: A semiconductor device includes first and second active cell regions and an inactive cell region between the first and second active cell regions, wherein each of the first and second active cell regions comprises: a trench gate; a first trench emitter; a first hole barrier layer of a first conductivity type formed between the trench gate and the first trench emitter; a base layer of a second conductivity type formed on upper portion of the first hole barrier layer; an emitter layer of the first conductivity type formed on upper portion of the base layer; a latch-up prevention layer of the second conductivity type formed on upper portion of the first hole barrier layer, wherein the inactive cell region comprises: a second trench emitter; a first floating layer of the second conductivity type formed between the trench gate of the first active cell region and the second trench emitter.

公开(公告)号：US20210151588A1

公开(公告)日：2021-05-20

申请号：US17082802

申请日：2020-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, first and second trench electrodes formed on the semiconductor substrate, a floating layer of a first conductivity type formed around the first and second trench electrodes, a floating separation layer of a second conductivity type formed between the first and second trench. electrodes and contacted with. the floating layer of the first conductivity type and a floating layer control gate disposed on the floating separation layer of the second conductivity type.

公开(公告)号：US20190035920A1

公开(公告)日：2019-01-31

申请号：US16020181

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

公开(公告)号：US20170005185A1

公开(公告)日：2017-01-05

申请号：US15145712

申请日：2016-05-03

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66348 ,  H03K17/127

Abstract: A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of p+ type semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of p+ type semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view.

Abstract translation: 半导体器件包括电连接到栅电极的第一沟槽栅极电极和第二沟槽栅极电极，以及电连接到发射极电极的第三沟槽栅电极和第四沟槽栅电极。 在第一沟槽栅极电极和第二沟槽栅电极之间的半导体层的一部分中形成多个p +型半导体区域。 多个p +型半导体区域在平面图中看时沿着第一沟槽栅电极的延伸方向彼此间隔开。

公开(公告)号：US20200259005A1

公开(公告)日：2020-08-13

申请号：US16859295

申请日：2020-04-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/417

Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.

公开(公告)号：US20180145134A1

公开(公告)日：2018-05-24

申请号：US15706554

申请日：2017-09-15

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0696 ,  H01L29/0619 ,  H01L29/083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397

Abstract: An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n+-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n+-type emitter regions are arranged in a staggered configuration in plan view.

公开(公告)号：US20180069109A1

公开(公告)日：2018-03-08

申请号：US15807978

申请日：2017-11-09

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H02M7/537 ,  H01L21/761 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66348 ,  H02M7/537

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

公开(公告)号：US20170092750A1

公开(公告)日：2017-03-30

申请号：US15271350

申请日：2016-09-21

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H02M7/537 ,  H01L29/66 ,  H01L21/761 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66348 ,  H02M7/537

Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

公开(公告)号：US20250098193A1

公开(公告)日：2025-03-20

申请号：US18780767

申请日：2024-07-23

Applicant: Renesas Electronics Corporation

Inventor： Nao NAGATA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/423

Abstract: According to one embodiment, the semiconductor device 1 includes a semiconductor substrate having an upper surface and a lower surface, and an emitter wiring, wherein when viewed from the upper surface side, the semiconductor substrate has an active region including a plurality of IGBTs, a termination region, and a main junction region, wherein the semiconductor substrate of the main junction region has an N− type drift layer and a P type junction impurity layer, wherein the semiconductor substrate of the termination region has an N− type drift layer and a P type floating layer, wherein at least the main junction region has a trench electrode provided inside the trench, and a trench insulating film provided between the trench electrode and the semiconductor substrate, and wherein the trench electrode and the P type junction impurity layer are connected to the emitter wiring.