-
公开(公告)号:US20250142975A1
公开(公告)日:2025-05-01
申请号:US18915623
申请日:2024-10-15
Applicant: Renesas Electronics Corporation
Inventor: Yasuyuki MORISHITA , Koki NARITA , Satoshi MAEDA
Abstract: A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.
-
公开(公告)号:US20180040609A1
公开(公告)日:2018-02-08
申请号:US15553138
申请日:2015-06-19
Applicant: Renesas Electronics Corporation
Inventor: Satoshi MAEDA , Yasuyuki MORISHITA , Masanori TANAKA
IPC: H01L27/02 , H01L23/528 , H01L23/50
Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.
-
公开(公告)号:US20130285207A1
公开(公告)日:2013-10-31
申请号:US13864464
申请日:2013-04-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Satoshi MAEDA , Maya UENO
IPC: H01L49/02
CPC classification number: H03B5/1237 , H01L27/0802 , H01L28/20 , H03K3/011 , H03K3/02 , H03K3/26 , H03L7/093
Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.
-
公开(公告)号:US20160204741A1
公开(公告)日:2016-07-14
申请号:US15077125
申请日:2016-03-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Satoshi MAEDA , Maya UENO
IPC: H03B5/24 , H03K3/011 , H01L27/092 , H01L27/06 , H01L49/02
CPC classification number: H03B5/1237 , H01L27/0802 , H01L28/20 , H03K3/011 , H03K3/02 , H03K3/26 , H03L7/093
Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.
-
公开(公告)号:US20150116047A1
公开(公告)日:2015-04-30
申请号:US14585283
申请日:2014-12-30
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Satoshi MAEDA , Maya UENO
IPC: H03B5/12
CPC classification number: H03B5/1237 , H01L27/0802 , H01L28/20 , H03K3/011 , H03K3/02 , H03K3/26 , H03L7/093
Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.
Abstract translation: 公开了一种半导体器件。 半导体器件包括具有由多个多晶硅电阻器形成的电阻器的功能电路,其功能电路的特性可以通过微调电阻来调整,并且其中多晶硅电阻器与每个多晶硅电阻串联或并联耦合 另一个并且沿垂直于半导体器件的一侧的方向布置。
-
-
-
-