公开(公告)号：US20230135511A1

公开(公告)日：2023-05-04

申请号：US17964284

申请日：2022-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koki NARITA

IPC: H01L27/02

Abstract: Breakdown of an internal element during an ESD application of a semiconductor device is suppressed. When static electricity is applied to an I/O signal pad, a discharge path is formed by an electrostatic protection mechanism. A gate switch circuit is arranged corresponding to a transistor to be protected having a drain electrically connected to the I/O signal pad. The gate switch circuit electrically connects a gate of the transistor to be protected to a first node having a potential higher than a potential of an I/O GND line when the discharge path is formed at the time of the application of static electricity to the I/O signal pad.

公开(公告)号：US20200185913A1

公开(公告)日：2020-06-11

申请号：US16654901

申请日：2019-10-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koki NARITA

IPC: H02H9/04 ,  H02H1/00 ,  H02M7/217 ,  H03K17/687 ,  H03F3/16

Abstract: The present invention provides both a margin of a discharge start voltage with respect to a power supply voltage and a margin of a clamp voltage with respect to a breakdown withstand voltage of an internal circuit. The semiconductor device according to the embodiment includes a first amplifier circuit for amplifying a detection signal and outputting a drive signa, a second amplifier circuit for feedback-amplifying the detection signal to be input to the first amplifier circuit, and a discharge element whose discharge capability changed according to the magnitude of the drive signal.

公开(公告)号：US20170047916A1

公开(公告)日：2017-02-16

申请号：US15170557

申请日：2016-06-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koki NARITA

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K19/00315

Abstract: A semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block, a first clamp circuit that clamps a potential difference between the second power supply voltage line and the first reference voltage line, a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit, and a second clamp circuit that clamps a potential difference between a line connected between the resistor circuit and the second circuit block and the first reference voltage line.

Abstract translation: 半导体器件包括连接在第一电源电压线和第一参考电压线之间的第一电路块，连接在第二电源电压线和第二参考电压线之间的第二电路块，并发送和接收信号 利用第一电​​路块，钳位第二电源电压线和第一参考电压线之间的电位差的第一钳位电路，连接在第二电源电压线和第二电路块之间的电阻电路， 电阻值大于第一钳位电路的阻抗;钳位电路，钳位电阻电路与第二电路块之间的电位与第一基准电压线之间的电位差。

公开(公告)号：US20160064373A1

公开(公告)日：2016-03-03

申请号：US14807735

申请日：2015-07-23

Applicant: Renesas Electronics Corporation

Inventor： Koki NARITA

IPC: H01L27/02 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L23/5221 ,  H01L27/0255 ,  H01L27/0277 ,  H01L27/0629 ,  H01L29/41758 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

Abstract translation: 半导体器件包括多个栅极电极和多个条状接触件，每个栅极电极沿着栅电极的长度方向与每个栅电极交替形成。 形成具有施加到形成源极和漏极之一的条状接触中的一个的参考电位的导电晶体管。 与形成源极和漏极中的另一个的条形触点中的一个相邻的栅极之一用作第一伪栅电极。 所述半导体器件还包括延伸在所述第一伪栅极上的金属，以将形成在所述第一伪栅电极的相对侧上的条形触点电连接在一起，以及连接到形成在所述第一伪栅电极的相对侧上的条形触点之一的焊盘 栅电极，其从导电晶体管设置在第一伪栅电极的两侧。

公开(公告)号：US20250142975A1

公开(公告)日：2025-05-01

申请号：US18915623

申请日：2024-10-15

Applicant: Renesas Electronics Corporation

Inventor： Yasuyuki MORISHITA ,  Koki NARITA ,  Satoshi MAEDA

IPC: H01L27/02 ,  H02H9/04

Abstract: A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.

公开(公告)号：US20180115156A1

公开(公告)日：2018-04-26

申请号：US15674692

申请日：2017-08-11

Applicant: Renesas Electronics Corporation

Inventor： Koki NARITA

IPC: H02H9/04 ,  H03K5/08 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0296 ,  H03K5/08

Abstract: According to an embodiment, a semiconductor integrated circuit includes a circuit block provided between a power source voltage line and a reference voltage line, a circuit block provided between a power source voltage line and a reference voltage line, a clamp unit which is provided between the power source voltage line and the reference voltage line and is conductive when it is detected that an ESD voltage is applied using a first time constant, a trigger circuit which causes a trigger signal to be active when it is detected that an ESD voltage is applied using a second time constant smaller than the first time constant, and a transistor which is provided between a signal line, between the circuit blocks, and the power source voltage line or the reference voltage line.

公开(公告)号：US20170207775A1

公开(公告)日：2017-07-20

申请号：US15473964

申请日：2017-03-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koki NARITA

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K19/00315

Abstract: A semiconductor device includes a first circuit block that is connected between a first power supply voltage line and a first reference voltage line, a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block, a first clamp circuit that clamps a potential difference between the second power supply voltage line and the first reference voltage line, a resistor circuit that is connected between the second power supply voltage line and the second circuit block and includes a resistance value that is greater than an impedance of the first clamp circuit, and a second clamp circuit that clamps a potential difference between a line connected between the resistor circuit and the second circuit block and the first reference voltage line.

公开(公告)号：US20250149881A1

公开(公告)日：2025-05-08

申请号：US18918189

申请日：2024-10-17

Applicant: Renesas Electronics Corporation

Inventor： Koki NARITA ,  Naoaki HIYAMA

IPC: H02H9/04 ,  H01L27/02

Abstract: A semiconductor device having a semiconductor chip with a first circuit, a second circuit, a third circuit, a first protection element, and a resistor circuit, the first circuit and the third circuit mutually input and output unidirectional or bidirectional signals via the second circuit, the first protection element is electrically connected to a first node which electrically connects a first terminal and the second circuit, and the resistor circuit is provided between the first node and a second node which electrically connects the first terminal, the first circuit, and the second circuit and is located upstream of the first node.

公开(公告)号：US20170179112A1

公开(公告)日：2017-06-22

申请号：US15446470

申请日：2017-03-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koki NARITA

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L27/0266 ,  H01L23/5221 ,  H01L27/0255 ,  H01L27/0277 ,  H01L27/0629 ,  H01L29/41758 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

公开(公告)号：US20160126942A1

公开(公告)日：2016-05-05

申请号：US14893059

申请日：2013-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koki NARITA

IPC: H03K17/081 ,  H03K5/08 ,  H02H9/04 ,  H01L27/02

CPC classification number: H03K17/08104 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/0629 ,  H01L27/0814 ,  H02H9/046 ,  H03K5/08

Abstract: A semiconductor integrated circuit device is provided with first and second regions that are operated by mutually different voltages, and a signal wiring that supplies a signal from the first region to the second region. The second region includes a circuit that is connected to between a first wiring to which a voltage is selectively supplied and a third terminal to which a voltage is supplied, and is operated by a differential voltage between the voltage in the first wiring and the voltage supplied to the third terminal, and a discharge circuit for discharging a charge in the first wiring. By using the discharge circuit, the potential difference between the signal wiring and the first wiring is prevented from becoming larger, and thus makes it possible to reduce damages of the circuit included in the second region.

Abstract translation: 半导体集成电路器件设置有由相互不同的电压操作的第一和第二区域以及从第一区域向第二区域提供信号的信号布线。 第二区域包括连接到选择供电电压的第一布线和供给电压的第三端子之间的电路，并且通过第一布线中的电压和所提供的电压之间的差分电压进行操作 到第三端子，以及用于放电第一布线中的电荷的放电电路。 通过使用放电电路，防止信号布线与第一布线之间的电位差变大，从而可以减少包括在第二区域中的电路的损坏。